NEC MuPD70F3187, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
(5) Counter clearing to 0000H through encoder clear input (pin TECRTn) (TTnIOC3 register bits
TTnSCE, TTnECS1, TTnECS0)
There are two methods to clear the counter to 0000H through TECRTn pin input, and encoder
clear input is controlled by bit TTnSCE. Bits TTnZCL, TTnBCL, TTnACL, TTnECS1, and
TTnECS0 are controlled by the setting of bit TTnSCE.
These clear methods are valid in the encoder compare mode.
<1> Method to clear counter to 0000H through detection of valid edge of TECRTn pin input
(TTnSCE = 0)
When TTnSCE = 0, the counter is cleared to 0000H in synchronization with the internal operation
clock upon detection of the valid edge set through TECRTn pin input edge detection specification.
At this time, an encoder clear interrupt (INTTTnEC) is output. When TTnSCE = 0, the setting of
bits TTnZCL, TTnBCL, and TTnACL are invalid.
Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn) Timings (1/4)
(a) When TTnSCE = 0, TTnECS1, 0 = 01B, TTnUDS = 11B are Set
Remark: n = 0, 1
TTnSCE TTnZCL TTnBCL TTnACL TTnECS1, 0 Method
0 Invalid Invalid Invalid
√
<1>
1
√ √ √
Invalid <2>
TENCTn0
TENCTn1
TECRTn
m
INTTTnEC
0 m + 1 1 2
Base clock
Count signal
Counter
Counter clear