NEC MuPD70F3187, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
11.4 Control Registers
(1) TMTn control register 0 (TTnCTL0)
TTnCTL0 is an 8-bit register that controls the operation of TMTn.
This register can be read and written in 8-bit or 1-bit units.
Reset input clears this register to 00H. Reset input clears this register to 00H.
When TTnCE = 1, only the TTnCE bit of the TTnCTL0 register can be changed. Perform write
access to the other bits using the same values.
Figure 11-6: TMTn Control Register 0 (TTnCTL0) (1/2)
Remark: n = 0, 1
After reset: 00H R/W Address: TT0CTL0 FFFFF690H,
TT1CTL0 FFFFF6A0H
7 6 5 4 3 2 1 0
TTnCTL0 TTnCE 0 0 0 0 TTnCKS2 TTnCKS1 TTnCKS0
(n = 0, 1)
TRnCE TMTn Operation Control
0 Internal operating clock operation disabled (TMTn reset asynchronously)
1 Internal operating clock operation enabled
When bit TTnCE is set to “0”, the internal operation clock of TMTn stops (fixed to low
level), and TMTn is reset asynchronously.
When bit TTnCE is set to “1”, the internal operation of TMTn is enabled from when bit
TTnCE was set to “1” and count-up is performed. The time until count-up is as listed in
Table TMTn Count Clock and Time Until Count-Up.
Remarks: 1. In the encoder compare mode, encoder capture mode, the functions that
are reset when TTnCE = 0 and TTnECC = 1 are as follows.
• Compare match detector (interrupt output low level)
• Timer output (Output inactive level)
• Edge detector for other than pins TENCTn0, TENCTn1, and TECRTn
2. The following functions are not reset.
• Counter
• Flags in TTnOPT1 register
• TTnCCR0 buffer, TTnCCR1 buffer register, counter read buffer register
• TENCTn0, TENCTn1, TECRTn pin edge detector
3. In modes other than the above, (in which TTnECC is fixed to 0), the
functions that are reset by TTnCE = 0 are as follows.
• Internal registers other than registers that can be written from the CPU,
and internal latch circuits