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PD75P308

SERIAL TRANSFER OPERATION

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

1600

KCY1

/2-50

150

400

250

Output

= 1k

Ω

, C

100pF*

KCY1

KH1,

KL1

SIK1

KSI1

KSO1

SCK Cycle Time

SCK High-, Low-Level Widths

SI Set-Up Time (vs. SCK )

SI Hold Time (vs. SCK )

SCK SO Output
Delay Time

↑

↓ →

*: R

and C

are load resistance and load capacitance of the SO output line.

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)

*: R

and C

are load resistance and load capacitance of the SO output line.

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

800

400

100

400

300

Input

= 1k

Ω

, C

100pF*

KCY2

KH2,

KL2

SIK2

KSI2

KSO2

↑

↓ →

★

↑

SCK Cycle Time

SCK High-, Low-Level Widths

SI Set-Up Time (vs. SCK )

SI Hold Time (vs. SCK )

SCK SO Output
Delay Time

Summary of Contents for mPD75P308

Page 1: ...ser s Manual IEM 5016 The function common to the one time PROM and EPROM types of product is referred to as PROM throughout this document The information in this document is subject to change without notice FEATURES µPD75308 compatible Memory capacity Program memory PROM 8064 x 8 bits Data memory RAM 512 x 4 bits Can be connected to a pull up resistor through software Ports 0 3 6 7 Open drain inpu...

Page 2: ...4 S3 S2 S1 S0 RESET P73 KR7 P72 KR6 P71 KR5 P70 KR4 P63 KR3 P62 KR2 P61 KR1 P60 KR0 X2 X1 V XT2 XT1 V P33 MD3 P32 MD2 P31 SYNC MD1 P30 LCDCL MD0 P23 BUS P22 PCL P21 P20 PTO0 P13 TI0 P12 INT2 P11 INT1 P10 INT0 P03 SI SBI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PP DD 25 26 27 28 29 30 31 32 33 34 35 BIAS P40 P41 P42 P43 P50 P51 P52 P53 V V V LCO LC1 LC2 V PD75P308GF 3...

Page 3: ... MEMORY RAM 512 x 4 BITS CY ALU VSS VDD VPP DECODE AND CONTROL PROGRAM MEMORY PROM 8064 x 8 BITS PROGRAM COUNTER 13 STAND BY CONTROL SYSTEM CLOCK GENERATOR CLOCK DIVIDER CLOCK OUTPUT CONTROL SUB MAIN f 2 X N X2 X1 XT2 XT1 PCL P22 CPU CLOCK INTERRUPT CONTROL BIT SEQ BUFFER 16 SERIAL INTERFACE WATCH TIMER TIMER EVENT COUNTER 0 BASIC INTERVAL TIMER TI0 P13 PTO0 P20 BUZ P23 SI SBI P03 SO SB0 P02 SCK P...

Page 4: ... AND µPD75308 10 3 WRITING AND VERIFYING PROM PROGRAM MEMORY 11 3 1 OPERATION MODES FOR WRITING VERIFYING PROGRAM MEMORY 11 3 2 PROGRAM MEMORY WRITE PROCEDURE 12 3 3 PROGRAM MEMORY READ PROCEDURE 13 3 4 ERASURE µPD75P308K ONLY 14 4 ELECTRICAL SPECIFICATIONS 15 5 PACKAGE DRAWINGS 28 6 RECOMMENDED SOLDERING CONDITIONS 30 APPENDIX A DEVELOPMENT TOOLS 31 APPENDIX B RELATED DOCUMENTS 32 ...

Page 5: ...oftware Input Input 1 bit output port BIT PORT Shared with a segment output pin G C 3 X F A F A Input Output Input Output Output Output Input Output Input Output With noise elimination function 4 bit input port PORT1 Internal pull up resistors can be specified in 4 bit units by software Programmable 4 bit input output port PORT3 This port can be specified for input output in bit units Internal pul...

Page 6: ...as a 1 bit input test pin System reset input low level active To select mode when writing verifying of program memory PROM Program voltage application when writing and verifying of program memory PROM Connect to VDD during the normal operation Apply 12 5V when writing verifying EPROM Positive power supply GND Input 1 2 NON PORT PINS TI0 Input P13 PTO0 Output P20 PCL Input Output P22 SCK Input Outp...

Page 7: ...N ch Push pull output that can be set in a output high impedance state both P ch and N ch are off IN Schmitt trigger input with hysteresis characteristics data output disable Type D Type A P U R enable VDD P U R P ch IN OUT P U R Pull Up Resistor P U R enable VDD P U R P ch TYPE B C TYPE E E IN P U R Pull Up Resistor P U R Pull Up Resistor Schmitt trigger input with hysteresis characteristics data...

Page 8: ...LC0 VLC1 VLC2 P ch N ch SEG data COM data OUT P ch N ch N ch P ch data output disable Type D Type B P U R enable VDD P ch IN OUT P U R Pull Up Resistor TYPE F B P U R Pull Up Resistor data output disable P U R enable VDD P U R P ch N ch P ch output disable P output disable N VDD IN OUT IN OUT N ch data output disable TYPE M A Middle voltage input buffer ...

Page 9: ...et This means that even during ordinary operation the µPD75P308 may be set in the test mode if a noise exceeding VDD is applied For example if the wiring length of the P00 INT4 or RESET pin is too long noise superimposed on the wiring line of the pin may cause the above problem Therefore keep the wiring length of these pins as short as possible to suppress the noise otherwise take noise preventive...

Page 10: ...ad of a mask ROM Programs can be rewritten to the PROM of the µPD75P308 Table 2 1 shows the differences between the µPD75P308 and µPD75308 You should fully consider these differences when you debug or produce your application system on an experimental basis by using the PROM model and then proceed to mass produce the system by using the mask ROM model For the details of the CPU and the internal ha...

Page 11: ...ted by the clock input through the X1 pin These pins input output 8 bit data when program memory is written verified VDD X1 X2 Note 1 Always cover the erasure window of the µPD75P308K with a light opaque film except when the contents of the program memory are erased 2 The one time PROM model µPD75P308GF is not equipped with a window and therefore the contents of the program memory of this model ca...

Page 12: ...has been written connectly proceed to step 10 If data has not yet been written repeat steps 7 to 9 10 Write additional data for the number of times data was written X in steps 7 to 9 times 1 milliseconds 11 Set program inhibit mode 12 Supply a pulse to the X1 pin four times to update the program memory address by 1 13 Repeat steps 7 to 12 to the last address 14 Set program memory address 0 clear m...

Page 13: ...lear mode 5 Supply 6 V to the VDD pin and 12 5 V to the VPP pin 6 Set program inhibit mode 7 Set verify mode Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times 8 Set program inhibit mode 9 Set program memory address 0 clear mode 10 Change the voltages of VDD and VPP pins to 5 V 11 Turn off the power supply Steps 2 to 9 are illustrated below VPP VD...

Page 14: ...ity 12 mW cm2 is used about 15 to 20 minutes is required Note 1 The contents of the program memory may be erased when the µPD75P308 is exposed for a long time to direct sunlight or the light of fluorescent lamps To protect the contents from being erased mask the window of the program memory with the light opaque film supplied as an accessory with the UV EPROM products 2 To erase the memory content...

Page 15: ...5 mA IOH All pins 30 mA Peak value 30 mA Effective value 15 mA Peak value 100 mA Effective value 60 mA Peak value 100 mA Effective value 60 mA Operating Temperature Topt 10 to 70 C Storage Temperature Tstg 65 to 150 C 1 The impedance of the power source pull up resistor must be 50 KΩ minimum when a voltage higher than 10V is applied to ports 4 and 5 2 Effective value Peak value x Duty One pin Tota...

Page 16: ...on frequency is 4 19 MHz fx 5 0 MHz do not select PCC 0011 as the instruction execution time otherwise one machine cycle is set to less than 0 95 µs falling short of the rated minimum value of 0 95 µs Caution When using the oscillation circuit of the main system clock wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity Keep the wiri...

Page 17: ...ross the wiring over the other signal lines Do not route the wiring in the vicinity of lines through which a high alternating current flows Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD Do not connect the power source pattern through which a high current flows Do not extract signals from the oscillation circuit The amplification factor of the ...

Page 18: ... Voltage Deviation Segment Supply Current 0 7 VDD VDD V 0 8 VDD VDD V 0 7 VDD 10 V VDD 0 5 VDD V 0 0 3 VDD V 0 0 2 VDD V 0 0 4 V VDD 1 0 VDD 2 0 V 0 4 V 1 0 V 3 µA 20 µA 20 µA 3 µA 20 µA 3 µA 20 µA 3 µA 2 5 VDD V 5 15 mA 500 1500 µA 350 1000 35 100 DC CHARACTERISTICS Ta 10 to 70 C VDD 5V 5 Parameter Symbol Conditions MIN TYP MAX Unit 0 4 2 0 V 0 2VDD V Pull up R 1kΩ VIN VDD VIN 0V VODC VODS I0 5 µ...

Page 19: ...High Low Level Widths RESET Low Level Width 0 95 64 µs 114 122 125 µs 0 1 MHz 0 48 µs 2 µs 10 µs 10 µs 0 1 2 3 4 5 6 0 5 1 2 3 4 5 6 60 64 70 with main system clock Cycle time t s cy µ Supply voltage V V DD t vs V cy DD 1 The CPU clock Φ cycle time is determined bytheoscillationfrequencyoftheconnected oscillator system clock control register SCC and processor clock control register PCC The figure ...

Page 20: ... vs SCK SI Hold Time vs SCK SCK SO Output Delay Time RL and CL are load resistance and load capacitance of the SO output line TWO LINE AND THREE LINE SERIAL I O MODES SCK external clock input RL and CL are load resistance and load capacitance of the SO output line Parameter Symbol Conditions MIN TYP MAX Unit 800 ns 400 ns 100 ns 400 ns 300 ns Input Input RL 1kΩ CL 100pF tKCY2 tKH2 tKL2 tSIK2 tKSI2...

Page 21: ...KSB tSBK tSBL tSBH RL and CL are load resistance and load capacitance of the SO output line SBI MODE SCK external clock output master RL and CL are load resistance and load capacitance of the SO output line RL 1kΩ CL 100pF SCK Cycle Time SCK High Low Level Widths SB0 1 Set Up Time vs SCK SB0 1 Hold Time vs SCK SCK SB0 1 Output Delay Time SCK SB0 1 SB0 1 SCK SB0 1 Low Level Width SB0 1 High Level W...

Page 22: ...AC TIMING TEST POINT excluding X1 and XT1 inputs Test points 0 8 VDD 0 2 VDD 0 8 VDD 0 2 VDD CLOCK TIMING X1 input VDD 0 5V 0 4 V tXL tXH 1 fX XT1 input VDD 0 5V 0 4 V tXTL tXTH 1 fXT TI0 tTIL tTIH 1 fTI TI0 TIMING ...

Page 23: ...µPD75P308 23 SERIAL TRANSFER TIMING THREE LINE SERIAL I O MODE SCK tKL1 tKH1 tKCY1 Output data tSIK1 tKSI1 tKSO1 Input data SI SO TWO LINE SERIAL I O MODE SCK tKL tKH tKCY tSIK tKSI SB0 1 tKSO ...

Page 24: ...TRANSFER RESET INPUT TIMING INT0 1 2 4 KR0 7 tINTL tINTH INTERRUPT INPUT TIMING SCK tKL3 4 tKCY3 4 tSIK3 4 tKSI3 4 tKSO3 4 SB0 1 tKH3 4 tSBK tKSB COMMAND SIGNAL TRANSFER RESET tRSL SCK tKL3 4 tKCY3 4 tSIK3 4 tKSI3 4 tKSO3 4 SB0 1 tKH3 4 tSBK tSBH tSBL tKSB ...

Page 25: ...ble operation when oscillation is started 3 Depends on the setting of the basic interval timer mode register BTM as follows BTM3 BTM2 BTM1 BTM0 WAIT time fX 4 19 MHz 0 0 220 fX approx 250 ms 0 1 217 fX approx 31 3 ms 1 0 215 fX approx 7 82 ms 1 1 213 fX approx 1 95 ms DATA RETENTION TIMING releasing STOP mode by RESET DATA RETENTION TIMING standby release signal releasing STOP mode by interrupt ST...

Page 26: ...PP Set Up Time vs MD3 VDD Set Up Time vs MD3 Initial Program Pulse Width Additional Program Pulse Width MD0 Set Up Time vs MD1 MD0 Data Output Delay Time MD1 Hold Time vs MD0 MD1 Recovery Time vs MD0 Program Counter Reset Time X1 Input High Low Level Width X1 Input Frequency Initial Mode Set Time MD3 Set Up Time vs MD1 MD3 Hold Time vs MD1 MD3 Set Up Time vs MD0 Address 2 Data Output Delay Time Ad...

Page 27: ...DS t tDS tDH t tDV tDF tDS tAH tAS tOPW t tM1R tPW tPCR tM1S tM1H tM3S tM3H tVPS tVDS t tDV tXH tXL tHAD tDAD Data output Data output tDFR tM3HR tPCR tM3SR tXH tXL I OH MOS I X1 P40 P43 P50 P53 VPP VDD VDD 1 VDD MD0 MD1 MD2 MD3 VPP VDD X1 P40 P43 P50 P53 PROGRAM MEMORY WRITE TIMING PROGRAM MEMORY READ TIMING ...

Page 28: ...0 35 0 10 0 15 20 0 0 2 0 929 0 016 0 039 0 031 0 006 0 031 T P 0 795 NOTE M N 0 15 0 15 1 8 0 2 0 8 T P 0 006 0 006 0 004 0 003 Each lead centerline is located within 0 15 mm 0 006 inch of its true position T P at maximum material condition 0 071 0 014 0 551 0 8 0 2 0 031 P 2 7 0 106 0 693 0 016 17 6 0 4 1 0 0 009 0 008 Q 0 1 0 1 0 004 0 004 S 3 0 MAX 0 119 MAX 0 10 0 05 0 009 0 008 0 004 0 005 0...

Page 29: ...A B C D E F G H I J K Q R S T U W 20 0 0 4 19 0 13 2 14 2 0 4 1 64 2 14 4 064 MAX 0 51 0 10 0 08 0 8 T P 1 0 0 2 C 0 5 0 8 1 1 R 3 0 12 0 0 75 0 2 0 787 0 748 0 520 0 559 0 016 0 065 0 084 0 160 MAX 0 020 0 004 0 003 0 031 T P 0 039 C 0 020 0 031 0 043 R 0 118 0 472 0 030 0 017 0 016 0 009 0 008 0 008 0 009 80 PIN CERAMIC WQFN A B D C T U F I M E G K Q J 80 R 1 H S W ...

Page 30: ...urs of pre baking is required at 125 C Infrared Reflow Package peak temperature 230 C IR30 162 1 time 30 seconds max 210 C min number of times 1 maximum number of days 2 days beyond this period 16 hours of pre baking is required at 125 C VPS Package peak temperature 215 C VP15 162 1 time 40 seconds max 200 C min number of times 1 maximum number of days 2 days beyond this period 16 hours of pre bak...

Page 31: ...P308K It is connected to PG 1500 Software IE Control Program Host machine PG 1500 Controller PC 9800 series MS DOSTM Ver 3 30 to Ver 5 00A 3 RA75X Relocatable IBM PC ATTM PC DOSTM Ver 3 1 Assembler APPENDIX A DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75P308 PROM writing tools EV 9200G 80 1 Maintenance product 2 Not pr...

Page 32: ...µPD75P308 32 APPENDIX B RELATED DOCUMENTS ...

Page 33: ... generated due to noise and an inrush current may flow through the device causing the device to malfunction Therefore fix the input level of the device by using a pull down or pull up resistor If there is a possibility that an unused pin serves as an output pin whose timing is not specified each pin should be connected to VDD or GND through a resistor Refer to Processing of Unused Pins in the docu...

Page 34: ...oration or others The devices listed in this document are not suitable for uses in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for the applications not intended by NEC please contact our sales people in advance Application examples...

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