NEC mPD75512 Datasheet Download Page 43

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PD75512

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

CALL

!addr

(SP-4)(SP-1)(SP-2)

←

11-0

(SP-3)

←

MBE, RBE, PC

13,12

13-0

←

addr, SP

←

SP-4

CALLF

!faddr

(SP-4)(SP-1)(SP-2)

←

11-0

(SP-3)

←

MBE, RBE, PC

13,12

13-0

←

00, faddr, SP

←

SP-4

RET

MBE, RBE, PC

13,12

←

(SP+1)

11-0

←

(SP)(SP+3)(SP+2)

←

SP+4

RETS

3+S

MBE, RBE, PC

13,12

←

(SP+1)

Undefined

11-0

←

(SP)(SP+3)(SP+2)

←

SP+4, then skip unconditionally

RETI

13,12

←

(SP+1)

11-0

←

(SP)(SP+3)(SP+2)

PSW

←

(SP+4)(SP+5), SP

←

SP+6

PUSH

(SP-1)(SP-2)

←

rp, SP

←

SP-2

(SP-1)

←

MBS, (SP-2)

←

RBS, SP

←

SP-2

POP

←

(SP+1)(SP), SP

←

SP+2

MBS

←

(SP+1), RBS

←

(SP), SP

←

SP+2

Inter-

IME (IPS.3)

←

rupt

IExxx

←

Control

IME (IPS.3)

←

IExxx

←

I/O

IN *

A,PORTn

←

PORT

(n = 0-15)

XA,PORTn

←

PORT

n+1

,PORT

(n = 4, 6)

OUT *

PORTn,A

PORT

←

(n = 2-7, 9-14)

PORTn,XA

PORT

n+1

,PORT

←

(n = 4, 6)

CPU

HALT

Set HALT Mode (PCC.2

←

Control

STOP

Set STOP Mode (PCC.3

←

NOP

No Operation

Special

RBn

RBS

←

n (n = 0-3)

MBn

MBS

←

n (n = 0, 1, 15)

GETI *

taddr

. Where TBR instruction,

*10

13-0

←

(taddr)

4-0

+(taddr+1)

. Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

←

11-0

(SP-3)

←

MBE, RBE, PC

13,12

13-0

←

(taddr)

5-0

+(taddr+1)

←

SP-4

. Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.

*2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of

GETI instruction.

Subrou-

tine/
Stack

Control

SEL

.........................................................

.............................

.........................................................

.............................

Summary of Contents for mPD75512

Page 1: ...nally provided Built in 8 bit A D converter 8 ch Variable instruction execution time function which is convenient for high speed operation and power saving 0 95 µs 1 95 µs 15 3 µs at 4 19 MHz operation 122 µs at 32 768 kHz operation Program memory ROM size 12 160 8 bits Data memory RAM size 512 4 bits High performance timer function 4 ch 8 bit timer event counter Clock timer 8 bit basic interval t...

Page 2: ...ed down by mask option 4 lines N ch Open Drain 20 lines capable of driving LED 8 lines 10 V withstand voltage pins that can be Input Outputs pulled up by mask option 20 A D Converter 8 bit resolution 8 channels successive approxmation type Operation voltage VDD 3 5 to 6 0 V Timer event counter Basic interval timer Timer pulse generator capable of outputting 14 bit PWM Watch timer NEC standard seri...

Page 3: ...N 15 5 MEMORY CONFIGURATION 16 6 PERIPHERAL HARDWARE FUNCTIONS 19 6 1 PORT 19 6 2 CLOCK GENERATOR CIRCUIT 20 6 3 CLOCK OUTPUT CIRCUIT 21 6 4 BASIC INTERVAL TIMER 22 6 5 WATCH TIMER 23 6 6 TIMER EVENT COUNTER 23 6 7 TIMER PULSE GENERATOR 25 6 8 SERIAL INTERFACE 26 6 9 A D CONVERTER 30 6 10 BIT SEQUENTIAL BUFFER 31 7 INTERRUPT FUNCTIONS 31 8 STANDBY FUNCTIONS 33 9 RESET FUNCTION 34 10 INSTRUCTION SE...

Page 4: ...µPD75512 4 13 PACKAGE DRAWINGS 63 14 RECOMMENDED SOLDERING CONDITIONS 64 APPENDIX A DEVELOPMENT TOOLS 65 APPENDIX B RELATED DOCUMENTS 66 ...

Page 5: ...00 P92 P91 P90 SI1 P83 SO1 P82 SCK1 P81 PPO P80 KR7 P73 KR6 P72 KR5 P71 KR4 P70 KR3 P63 KR2 P62 KR1 P61 KR0 P60 P53 P52 P51 P50 V SS P43 P42 P41 P40 P33 P32 P31 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P140 P141 P142 P143 RESET X2 X1 IC XT2 XT1 VSS P00 INT4 P01 SCK0 P02 SO0 SB0 P03 SI0 SB1 P10 INT0 P11 INT1 P12 INT2 P13 TI0 P20 PTO0 P21 P22 PCL P23 BUZ P30 79 78 77 76 7...

Page 6: ...age synthesizer tuner PD75512 µ Remote control IC Mechanism Servo IC INT0 Input port Output port Mechanism control Mechanical controller Timer SIO Analog input PPO Key matrix Port4 5 KR0 KR7 SIO OSD LPF FIP driver Tuner FIP Clock for clock System clock ...

Page 7: ...RAM DATA MEMORY 512 x 4 BITS TI0 P13 TIMER EVENT COUNTER 0 INTT0 PTO0 P20 BUZ P23 WATCH TIMER INTW INTCSI SERIAL INTERFACE0 SI0 SB1 P03 SO0 SB0 P02 SCK0 P01 INT0 P10 INT1 P11 INT2 P12 INT4 P00 KR0 P60 KR7 P73 8 INTERRUPT CONTROL BIT SEQ BUFFER 16 BASIC INTERVAL TIMER INTBT PPO P80 TIMER PULSE GENERATOR INTTPG SERIAL INTERFACE1 SI1 P83 SO1 P82 SCK1 P81 A D CONVERTER AVREF AVSS AN0 AN3 AN4 P150 AN7 ...

Page 8: ...specified in output bit units x Input E C P32 2 Built in pull up resistors can be specified by software in 4 bit unit P33 2 N ch open drain 4 bit input output High level port PORT4 when pull up P40 to Input A pull up resistor can be provided resistor is M P43 2 output in bit units mask option provided or 10V withstanding voltage in the high impedance open drain mode O N ch open drain 4 bit input o...

Page 9: ...ut N ch open drain 4 bit input output High level port PORT12 when pull up P120 to Input A pull up resistor can be provided resistor is M P123 output in bit units mask option x provided or 10V withstanding voltage in the high impedance open drain mode N ch open drain 4 bit input output High level port PORT13 when pull up P130 to Input A pull up resistor can be provided x resistor is M P133 output i...

Page 10: ...ion KR0 KR3 Input P60 P63 Parallel falling edge detection testable input pin Input F C KR4 KR7 Input P70 P73 Parallel falling edge detection testable input pin Input F A SCK1 Input P81 Serial clock input output pin Input F output SO1 Output P82 Serial data output pin Input E SI1 Input P83 Serial data input pin Input B AN0 AN3 Y Input A D converter analog input pin AN4 AN7 P150 P153 Y A AVREF Input...

Page 11: ...gh impedance state both P ch and N ch are off IN Schmitt trigger input with hysteresis characteristics data output disable Type D Type A IN OUT This input output circuit consists of D type push pull outputs and Type A input buffers P U R enable VDD P U R P ch TYPE B C TYPE E B IN data output disable Type D Type A P U R enable VDD P U R P ch IN OUT Schmitt trigger input with hysteresis characterist...

Page 12: ...a output disable Type D Type B IN OUT This input output circuit consists of D type push pull outputs and Type B Schmitt trigger inputs Type F A Type M data output disable VDD P U R IN OUT N ch Middle voltage input buffer can withstand up to 10 V data output disable Type D Type A P U R enable VDD P U R P ch IN OUT can withstand up to 10 V P U R Pull Up Resistor P U R Pull Up Resistor P U R Pull Up ...

Page 13: ...ce voltage from a voltage tap of series resistor string IN instruction data output disable Type D Type A IN OUT AV AVSS Reference voltage REF P D R Mask Option N ch IN P ch AVSS V DD V DD AVSS Sampling C Input enable Reference voltage from a voltage tap of series resistor string P U R Pull Up Resistor P U R Pull Up Resistor Type Y Fig 4 1 Pin Input Output Circuits 3 3 ...

Page 14: ...Connect to VSS P13 TI0 P20 PTO0 P21 P22 PCL P23 BUZ Input state Connect to VSS or VDD P30 P33 Output state Open P40 P43 P50 P53 P60 KR0 P63 KR3 P70 KR4 P73 KR7 P80 PPO P81 SCK1 Connect to VSS or VDD P82 SO1 P83 SI1 P90 P93 P100 P103 P110 P113 Input state Connect to VSS or VDD P120 P123 Output state Open P130 P133 P140 P143 P150 AN4 P153 AN7 Connect to VSS AN0 AN3 XT1 Connect to VSS or VDD XT2 Open...

Page 15: ...33 P140 P143 P90 P93 1 With pull down resistor 2 Without pull down resistor Can be specified in bit units Can be specified in bit units 2 Feedback resistor selection for the subsystem clock oscillation Table 4 3 Feedback Resistor Selection Pins Mask Option XT1 XT2 1 With feedback resistor 2 Without feedback resistor When the subsystem clock When the subsystem clock is used is not used Note The ope...

Page 16: ...ch address from which program is started is written after reset 0002H 000DH Vector table to which address from which program is started is written after interrupt 0020H 007FH Table area referenced by GETI instruction Data memory Data area 512 words 4 bits 000H 1FFH Peripheral hardware area 128 words 4 bits F80H FFFH ...

Page 17: ...H 1000H 1FFFH GETI instruction reference table 0 CALLF faddr instruction entry address Address 2000H 2F7FH BRCB caddr instruction branch address BRCB caddr instruction branch address RBE RBE RBE RBE RBE RBE MBE INTTPG start address upper 6 bits 000CH RBE INTTPG start address lower 8 bits BR addr instruction branch address CALL addr instruction subroutine entry address BR addr instruction relationa...

Page 18: ...a memory Memory bank General purpose register area 000H 01FH 008H 32 4 256 4 Stack area 100H 0FFH Data area Static RAM 512 4 1FFH 256 4 Unmapped F80H 128 4 FFFH Peripheral hardware area 15 1 0 Fig 5 2 Data Memory Map ...

Page 19: ...10V Can be specified for I O in 1 4 bit units Ports 6 and 7 can Also serves as KR0 3 4 bit I O be paired to I O Can be specified data in 8 bit units I O in 4 bit Also serves as KR4 7 units 4 bit Can be read or tested regardless of the operation Also serves as PPO SCK1 input mode of the shared pin SO1 and SI1 pins Whether or not the internal pull up resistor is provided can be specified for each bi...

Page 20: ...terrupt control circuit Timer pulse generator 6 2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser PPC and system clock control register SCC This circuit can generate two types of clocks main system clock and subsystem clock In addition it can also change the instruction execution time 0 95 µs 1 91 µs 15 3 µs main system cloc...

Page 21: ...t 4 19 MHz Buzzer output BUZ 2 kHz operating at 4 19 MHz or 32 768 kHz Selector Output buffer PCL P22 Bit 2 of PMGB PORT2 2 Port 2 input output mode specification bit P22 output latch Internal bus CLOM3 CLOM2 CLOM1 CLOM0 CLOM 4 Φ fX 23 fX 24 fX 26 From the clock generator Fig 6 2 Clock Output Circuit Configuration Remarks A measures to prevent outputting narrow width pulse when selecting clock out...

Page 22: ... runaway Selects the wait time for releasing the standby mode and counts the wait time Reads out the count value From the clock generator fX 25 fX 27 fX 29 fX 212 MPX Clear Basic interval timer 8 bit frequency divider circuit 3 4 8 BT Clear Set signal BT interrupt request flag IRQBT Wait release signal for standby release Vector interrupt request signal Internal bus BTM3 BTM2 BTM1 BTM0 BTM SET1 In...

Page 23: ...0 0 WM2 WM1 WM0 Selector Frequency divider f W 2 7 256 Hz 3 91 ms INTW IRQW set signal f W 2 14 2 Hz 0 5 sec Selector f W 32 768 kHz f W 16 2 048 kHz Clear f X 128 32 768 kHz f XT 32 768 kHz From the clock generator WM PORT2 3 Bit 2 of PMGB Output buffer P23 BUZ P23 output latch Port 2 input output mode Bit test instruction 8 Internal bus Remarks is for fX 4 194304 MHz fXT 32 768 kHz Fig 6 4 Watch...

Page 24: ...imer operation start signal CP 8 8 Modulo register 8 Comparator 8 Count register 8 Clear T0 TMOD0 Reset TOE0 PORT2 0 Bit 2 of PGMB To serial interface P20 PTO0 INTT0 IRQT0 set signal RESET IRQT0 clear signal Output buffer TOUT F F TO enable flag P20 output latch Port 2 input output mode Coinci dence 8 Fig 6 5 Timer Event Counter Block Diagram Refer to Fig 4 11 ...

Page 25: ...nterval interrupt generation 2 15 fX 7 81ms fX 4 19 MHz When no pulse output is required the PPO pin can be used as 1 bit output port Note When setting the STOP mode if the timer pulse generator is in operating mode erroneous operation may occur Therefore the timer pulse generator must be set in no operation state by the mode register before setting the STOP mode Internal bus 8 8 TPGM3 Set to 1 MO...

Page 26: ...l 0 and channel 1 Table 6 2 Differences Between Channel 0 and Channel 1 Serial Transfer Mode Funciton Channel 0 Channel 1 Clock Selection fX 2 4 fX 2 3 TOUT F F external clock fX 2 4 fX 2 3 external clock 3 Line Transfer Method MSB first LSB first selectable MSB first Serial I O Transfer Completion Serial transfer completion interrupt Serial transfer completion flag EOT Flag request flag IRQCSI0 2...

Page 27: ...n 8 8 Coincidence signal SBIC RELT CMDT SO0 latch Bit test ACKT ACKE BSYE Busy acknowledge output circuit Bus release command acknowledge detector circuit RELD CMDD ACKD Serial clock counter Serial clock control circuit INTCSI0 control circuit MPX INTCSI0 IRQCSI0 set signal D Q fX 23 fX 24 fX 26 TOUT F F from timer event counter External SCK0 8 Fig 6 8 Serial Interface Channel 0 Block Diagram CSIM...

Page 28: ...µPD75512 28 2 Serial interface Channel 1 configuration µPD75512 serial interface channel 1 has following two modes Operation stop mode 3 line serial I O mode ...

Page 29: ...IM1 Clear Set Serial transfer completion flag EOT f 2 x 3 f 2 x 4 MPX 8 Bit manipulation bit 7 Serial operation mode 8 register 1 8 Internal bus 8 SIO1 write signal serial start signal SIO1 7 bit 0 Shift register 1 8 P83 SI1 P82 SO1 P81 SCK1 Serial clock counter 3 Overflow Clear Q R S ...

Page 30: ...hannels of analog inputs AN0 AN7 This A D converter is of a successive approximation type AN0 AN1 AN2 AN3 AN4 AN5 AVREF AVSS Multiplexer Sample hold circuit Tap decoder R 2 R 2 R R R 8 8 SA register 8 Control circuit Internal bus 0 ADM6 ADM5 ADM4 SOC EOC ADM1 0 ADM Comparator 8 AN6 AN7 Fig 6 10 Block Diagram of A D Converter ...

Page 31: ...t Sequential Buffer Format 7 INTERRUPT FUNCTIONS The µPD75512 has 7 different interrupt sources and multiplexed interrupt with priority order In addition to that the µPD75512 is also provided with two types of test sources of which INT2 has two types of edge detection testable inputs The interrupt control circuit of the µPD75512 has these functions Hardware controlled vector interrupt function whi...

Page 32: ... Both edge detection circuit Edge detection circuit Edge detection circuit Rising edge detection circuit Falling edge detection circuit IRQ4 IRQ0 IRQ1 IRQCSI0 IRQT0 IRQTPG IM2 Interrupt enable flag IExxx IME VRQn Decoder IST Priority control circuit Vector table address generator Standby release signal Fig 7 1 Interrupt Control Block Diagram IRQ2 INTW IRQW 4 2 IPS ...

Page 33: ...BT with the reference time interval System Clock at the Time of Setting Serial Interface Channel 0 Operates when the timer system clock is operating or external SCK0 is selected Serial Interface Channel 1 Can operate only when the external SCK1 input is selected as the serial clock Operates only when the main system clock is operating Timer Event Counter Can only operate when the TI0 pin input is ...

Page 34: ... 0 Same as left PSW Carry Flag CY Retained Undefined Skip Flag SK0 2 0 0 Interrupt Status Flag IST0 1 0 0 Bank Enable Flag MBE RBE The contents of bit 6 of address 0000H of the program memory are set to RBE and those of bit 7 are set to MBE Same as left Stack Pointer SP Undefined Undefined Data Memory RAM Retained Undefined General Purpose Register X A H L D E B C Retained Undefined Bank Selection...

Page 35: ...Retained Undefined Interface SIO1 Channel 1 Operation Mode 0 0 Register 1 CSIM1 Serial Transfer End 0 0 Flag EOT Interrupt Interrupt Request Flag Reset 0 Reset 0 Function IRQxxx Interrupt Enable Flag 0 0 IExxx Interrupt Master Enable 0 0 Flag IME INT0 INT1 INT2 Mode 0 0 0 0 0 0 Registers IM0 1 2 Digital Port Output Buffer Off Off Output Latch Clear 0 Clear 0 Input Output Mode 0 0 Register PMGA B C...

Page 36: ...iption reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL rpa1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or label bit 2 bit immediate data or label fmem FB0H to FBFH FF0H to FFFH immediate data or label pmem FC0H to FFFH immediate data or label ad...

Page 37: ...Register pair HL 8 bit accumulator XA Expanded register pair XA BC Expanded register pair BC DE Expanded register pair DE HL Expanded register pair HL PC Program counter SP Stack pointer CY Carry flag or bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 0 to 15 IME Interrupt mask enable flag IPS Interrupt priority selector register IEx...

Page 38: ...ank that can be accessed 2 In 2 MB 0 regardless of MBE and MBS 3 In 4 and 5 MB 15 regardless of MBE and MBS 4 6 to 10 indicate areas that can be addressed 4 Machine cycle field In this field S indicates the number of machine cycles required when an instruction having a skip function skips The value of S varies as follows When no instruction is skipped S 0 When 1 byte or 2 byte instruction is skipp...

Page 39: ...S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp1 XA XCH A HL 1 1 A HL 1 A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 A mem 2 2 A mem 3 XA mem 2 2 XA m...

Page 40: ...rry XA rp 2 2 S XA XA rp carry rp 1 XA 2 2 S rp 1 rp 1 XA carry A HL 1 1 A CY A HL CY 1 ADDC XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY A HL 1 1 S A A HL 1 borrow SUBS XA rp 2 2 S XA XA rp borrow rp 1 XA 2 2 S rp 1 rp 1 XA borrow A HL 1 1 A CY A HL CY 1 SUBC XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY A n4 2 2 A A n4 AND A HL 1 1 A A HL 1 XA rp 2 2 XA XA rp rp 1 XA 2 2 rp ...

Page 41: ...L 1 1 HL 0 ment mem 2 2 S mem mem 1 3 mem 0 DECS reg 1 1 S reg reg 1 reg FH rp 2 2 S rp rp 1 rp FFH Compari reg n4 2 2 S Skip if reg n4 reg n4 son HL n4 2 2 S Skip if HL n4 1 HL n4 SKE A HL 1 1 S Skip if A HL 1 A HL XA HL 2 2 S Skip if XA HL 1 XA HL A reg 2 2 S Skip if A reg A reg XA rp 2 2 S Skip if XA rp XA rp SET1 CY 1 1 CY 1 CLR1 CY 1 1 CY 0 SKT CY 1 1 S Skip if CY 1 CY 1 NOT1 CY 1 1 CY CY Car...

Page 42: ...m L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 0 5 pmem L 0 H mem bit 2 2 S Skip if H mem3 0 bit 0 1 H mem bit 0 SKTCLR fmem bit 2 2 S Skip if fmem bit 1 and clear 4 fmem bit 1 pmem L 2 2 S Skip if pmem7 2 L3 2 bit 5 pmem L 1 L1 0 1 and clear H mem bit 2 2 S Skip if H mem3 0 bit 1 and clear 1 H mem bit 1 AND1 CY fmem bit 2 2 CY CY fmem bit 4 CY pmem L 2 2 CY CY pmem7 2 L3 2 bit L1 0 5 CY H mem bit 2 2 CY...

Page 43: ...upt IExxx 2 2 IExxx 1 Control DI 2 2 IME IPS 3 0 IExxx 2 2 IExxx 0 I O IN 1 A PORTn 2 2 A PORTn n 0 15 XA PORTn 2 2 XA PORTn 1 PORTn n 4 6 OUT 1 PORTn A 2 2 PORTn A n 2 7 9 14 PORTn XA 2 2 PORTn 1 PORTn XA n 4 6 CPU HALT 2 2 Set HALT Mode PCC 2 1 Control STOP 2 2 Set STOP Mode PCC 3 1 NOP 1 1 No Operation Special RBn 2 2 RBS n n 0 3 MBn 2 2 MBS n n 0 1 15 GETI 2 taddr 1 3 Where TBR instruction 10 ...

Page 44: ...l of ports 5 11 Peak 100 mA rms 60 mA Total of ports 12 14 Peak 40 mA rms 25 mA Operating Temperature Topt 40 to 85 C Storage Temperature Tstg 65 to 150 C rms Peak value x Duty OPERATING SUPPLY VOLTAGE Parameter Symbol Conditions MIN MAX Unit A D Converter Supply voltage VDD 3 5 6 0 V Ambient temperature Ta 10 70 C Timer Pulse Supply voltage VDD 4 5 6 0 V Generator Ambient temperatuare Ta 40 85 C ...

Page 45: ...ator Recommended Item Conditions MIN TYP MAX Unit Constants Crystal Oscillation 1 32 32 768 35 kHz frequency fXT Oscillation stabiliza VDD 4 5 to 6 0 V 1 0 2 s tion time 2 10 s External Clock XT1 input frequency 32 100 kHz fXT 1 XT1 input high low level widths 5 15 µs tXTH tXTL 1 Only to express the characteristics of the oscillator circuit For instruction execution time refer to AC Characteristic...

Page 46: ...urrent dissipation and therefore the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit When using the subsystem clock therefore exercise utmost care in wiring the circuit RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK CERAMIC OSCILLATOR Ta 40 to 85 C External Capacitor pF Oscillation Voltage Range V Manufacturer Produ...

Page 47: ... VDD 4 5 to 6 0 V 0 4 2 0 V Voltage IOL 15 mA VDD 4 5 to 6 0 V IOL 1 6 mA 0 4 V IOL 400 µA 0 5 V SB0 1 Open drain Pull up 0 2VDD V resistor 1 kΩ High Level Input ILIH1 VI VDD Other than below 3 µA Leakage Current ILIH2 X1 X2 XT1 20 µA ILIH3 VI 9 V Ports 4 5 12 14 20 µA open drain Low Level Input ILIL1 VI 0 V Other than below 3 µA Leakage Current ILIL2 X1 X2 XT1 20 µA High Level Output ILOH1 VO VDD...

Page 48: ...D4 HALT mode VDD 3 V 10 5 15 µA IDD5 XT1 0 V VDD 5 V 10 0 5 20 µA STOP mode VDD 3 V 10 0 3 10 µA Ta 25 C 5 µA 1 Currents for the built in pull up resistor are not included 2 Including when the subsystem clock is operated 3 When operand in the high speed mode with the processor clock control register PCC set to 0011 4 When operated in the low speed mode with the PCC set to 0000 5 When operated with...

Page 49: ... 10 µs KR0 7 10 µs RESET Low Level Width tRSL 10 µs 1 The CPU clock Φ cycle time is determined by the oscillation frequency of the connected oscillator system clock control register SCC and processor clock control register PCC The figure on the right is cycle time tCY vs supply voltage VDD characteristics at the main system clock 2 2tCY or 128 fX depending on the setting of the interrupt mode regi...

Page 50: ...K1 150 ns SI Hold Time vs SCK tKSI1 400 ns SCK SO Output tKSO1 RL 1 kΩ VDD 4 5 to 6 0 V 250 ns Delay Time CL 100 pF 1000 ns RL and CL are load resistance and load capacitance of the SO output line Parameter Symbol Conditions MIN TYP MAX Unit SCK Cycle Time tKCY2 VDD 4 5 to 6 0 V 800 ns 3200 ns SCK High Low Level tKL2 VDD 4 5 to 6 0 V 400 ns Widths tKH2 1600 ns SI Set Up Time vs SCK tSIK2 100 ns SI...

Page 51: ...Y3 ns SB0 1 High Level Width tSBH tKCY3 ns RL and CL are load resistance and load capacitance of the SO output line d SBI Mode SCK external clock input slave Parameter Symbol Conditions MIN TYP MAX Unit SCK Cycle Time tKCY4 VDD 4 5 to 6 0 V 800 ns 3200 ns SCK High Low Level tKL4 VDD 4 5 to 6 0 V 400 ns Widths tKH4 1600 ns SB0 1 Set Up Time tSIK4 100 ns vs SCK SB0 1 Hold Time tKSI4 tKCY4 2 ns vs SC...

Page 52: ...t Impedance RAN 1000 MΩ AVREF Current IREF 1 0 2 0 mA 1 Absolute accuracy excluding quantization error 1 2 LSB 2 Set ADM1 as follows in respect to the reference voltage of the AD converter AVREF ADM1 can be set to either 0 or 1 when 0 6VDD AVREF 0 65VDD 3 Time since execution of conversion start instruction until EOC 1 40 1 µs fX 4 19 MHz 4 Time since execution of conversion start instruction unti...

Page 53: ...AC TIMING TEST POINT excluding X1 and XT1 inputs X1 input VDD 0 5V 0 4 V tXL tXH 1 fX XT1 input VDD 0 5V 0 4 V tXTL tXTH 1 fXT TI0 tTIL tTIH 1 fTI CLOCK TIMING TI0 TIMING Test points 0 8 VDD 0 2 VDD 0 8 VDD 0 2 VDD ...

Page 54: ...µPD75512 54 SERIAL TRANSFER TIMING THREE LINE SERIAL I O MODE SCK tKL1 tKH1 tKCY1 Output data tSIK1 tKSI1 tKSO1 Input data SI SO TWO LINE SERIAL I O MODE SCK tKL2 tKH2 tKCY2 tSIK2 tKSI2 tKSO2 SB0 1 ...

Page 55: ...NAL SCK tKL3 4 tKCY3 4 tSIK3 4 tKSI3 4 tKSO3 4 SB0 1 tKH3 4 tSBK tSBH tSBL tKSB COMMAND SIGNAL TRANSFER SCK tKL3 4 tKCY3 4 tSIK3 4 tKSI3 4 tKSO3 4 SB0 1 tKH3 4 tSBK tKSB INTERRUPT INPUT TIMING INT0 1 2 4 KR0 7 tINTL tINTH RESET INPUT TIMING RESET tRSL ...

Page 56: ...Current 1 Release Signal Set Time tSREL 0 µs Oscillation Stabilization tWAIT Released by RESET 217 fX ms Wait Time 2 Released by interrupt 3 ms 1 Does not include current flowing through internal pull up resistor 2 The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started 3 Depends on the setting of the basic inter...

Page 57: ...tal oscillator 4 19 MHz Crystal oscillator 32 768 kHz C4 X1 X2 XT1 XT2 Main system clock HALT mode Low speed mode PCC 0000 Middle speed mode PCC 0010 High speed mode PCC 0011 T 25 C a Operating current I A DD µ Operating voltage V V DD Main system clock STOP mode 32 kHz oscillation and subsystem clock HALT mode Subsystem clock Operation mode ...

Page 58: ...CC 0000 Middle speed mode PCC 0010 High speed mode PCC 0011 T 25 C a Operating current I A DD µ Operating voltage V V DD Main system clock STOP mode 32 kHz oscillation and subsystem clock HALT mode Subsystem clock Operation mode Ceramic oscillator 4 19 MHz Crystal oscillator 32 768 kHz C1 C2 C3 C4 When compared to crystal oscillation increased by approximately 10 ...

Page 59: ...m clock HALT mode Low speed mode PCC 0000 Middle speed mode PCC 0010 High speed mode PCC 0011 T 25 C a Operating current I A DD µ Operating voltage V V DD Main system clock STOP mode 32 kHz oscillation and subsystem clock HALT mode Subsystem clock Operation mode C1 C2 C3 Ceramic oscillator 2 0 MHz Crystal oscillator 32 768 kHz C4 ...

Page 60: ...m clock HALT mode T 25 C a Operating current I A DD µ Operating voltage V V DD Main system clock STOP mode 32 kHz oscillation and subsystem clock HALT mode Subsystem clock Operation mode Low speed mode PCC 0000 Middle speed mode PCC 0010 High speed mode PCC 0011 C1 C2 C3 Ceramic oscillator 1 0 MHz Crystal oscillator 32 768 kHz C4 ...

Page 61: ... 1 2 3 4 5 X1 X2 High speed mode PPC 0011 Middle speed mode PPC 0010 Low speed mode PPC 0000 Main system clock HALT mode T 25 C a 40 30 20 10 0 1 2 3 4 5 V V OL V 6V DD V 5V DD V 4V DD V 3V DD V 2 7V DD VOL vs IOL T 25 C a Port 3 4 5 40 30 20 10 0 1 2 3 4 5 V 6V DD V 5V DD V 4V DD V 3V DD V 2 7V DD I mA DD High speed mode PPC 0011 IDD vs fx I mA DD f MHz x I mA OL V V OL VOL vs IOL Port 0 2 6 7 ...

Page 62: ...µPD75512 62 VOH vs IOH 15 10 5 0 I mA OH 20 1 2 3 4 5 V V V DD OH V 5V DD V 3V DD V 4V DD V 2 7V DD V 6V DD T 25 C a ...

Page 63: ...0 35 0 10 0 15 20 0 0 2 0 929 0 016 0 039 0 031 0 006 0 031 T P 0 795 NOTE M N 0 15 0 15 1 8 0 2 0 8 T P 0 006 0 006 0 004 0 003 Each lead centerline is located within 0 15 mm 0 006 inch of its true position T P at maximum material condition 0 071 0 014 0 551 0 8 0 2 0 031 P 2 7 0 106 0 693 0 016 17 6 0 4 1 0 0 009 0 008 Q 0 1 0 1 0 004 0 004 S 3 0 MAX 0 119 MAX 0 10 0 05 0 009 0 008 0 004 0 005 0...

Page 64: ...erature 230 C IR30 00 1 time 30 seconds max 210 C min number of times 1 VPS Package peak temperature 215 C VP15 00 1 time 40 seconds max 200 C min number of times 1 Wave Soldering Soldering bath temperature 260 C max WS60 00 1 time 10 seconds max number of times 1 pre heating temperature 120 C max package surface temperature Pin Partial Heating Pin temperature 300 C max time 3 seconds max per side...

Page 65: ...on socket EV 9200G 80 PG 1500 PROM programmer PA 75P516GF PROM programmer adapter solely used for µPD75P516GF It is connected to PG 1500 Software IE Control Program PG 1500 Controller RA75X Relocatable Assembler 1 Maintenance product 2 Not provided with IE 75001 R 3 Ver 5 00 5 00A has a task swap function but this function cannot be used with this software Remarks For development tools from other ...

Page 66: ...µPD75512 66 APPENDIX B RELATED DOCUMENTS ...

Page 67: ...generated due to noise and an inrush current may flow through the device causing the device to malfunction Therefore fix the input level of the device by using a pull down or pull up resistor If there is a possibility that an unused pin serves as an output pin whose timing is not specified each pin should be connected to VDD or GND through a resistor Refer to Processing of Unused Pins in the docum...

Page 68: ...on or others The devices listed in this document are not suitable for uses in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for the applications not intended by NEC please contact our sales people in advance Application examples reco...

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