CHAPTER 3 NOTES ON TARGET SYSTEM DESIGN
User’s Manual U16647EJ1V0UM
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3.2
Interface Signals
This section describes the interface signals.
3.2.1 DRST
This is the reset input signal for the on-chip debug unit. This is a negative logic signal for initializing the debug
control unit asynchronously. Barring a problem arising from the specifications of the target device, pull down this
signal to low level.
Figure 3-2. DRST Pin Connection Example
74LV125A
DRST
IE-V850E1-CD-NW
22
Ω
Target device
V
DD
Target system
DRST
Upon detection of V
DD
of the target system following integrated debugger startup by the IE-V850E1-CD-NW, the
DRST signal changes from low level to high level to start the on-chip debug unit of the target device.
The change of the DRST signal from low level to high level also resets the CPU.
When debugging is started by starting up the integrated debugger, CPU reset always occurs.
3.2.2 DCK
This is the clock input signal. This signal supplies a 20 MHz clock from the IE-V850E1-CD-NW. The DMS and DDI
signals are sampled in synchronization with the rising edge of the DCK signal in the on-chip debug unit, and the data
DDO signal is output in synchronization with the falling edge of the DCK signal. Barring a problem arising from the
specifications of the target device, pull up this signal to high level.
Figure 3-3. DCK Pin Connection Example
74LV125A
DCK
IE-V850E1-CD-NW
22
Ω
Target device
V
DD
Target system
V
DD
DCK
