CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
User’s Manual U16556EJ1V0UM
34
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to that of the
µ
PD784938A
Subseries. Their AC characteristics and DC characteristics are therefore different from
µ
PD784938A Subseries,
making it necessary to observe a stricter timing design than in the case of
µ
PD784938A Subseries.
•
RESET signal
•
Signals related to clock input
Figure 4-2. Equivalent Circuit 2 of Emulation Circuit
LV
CC
4.7 k
Ω
V
CC
4.7 k
Ω
24
Ω
ALTERA
EPM7128-15
VHC244
RESET
RESET
VHC244
CLK IN
X1
X2
Input
Output
Open
IE-784937-NS-EM1
UMCLK mounted clock
ACT86
RZT025P
Input
Output
ACT86
RZT025P
Multiplier
Multiplier
1
2
3
JP3
ALS157
ALS157
Remark
When using the IE-784937-NS-EM1 with the IE-78K4-NS, set JP3 with 1 and 2 shorted.
