User’s Manual U16043EJ2V0UM
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CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
This chapter describes differences between the target device’s signal lines and the signal lines of the IE-178054-
NS-EM1’s target interface circuit.
Although the target device is a CMOS circuit, the IE-178054-NS-EM1’s target interface circuit consists of an
emulation CPU, emulation gate array, TTL, CMOS-IC, and other components.
When the IE system is connected with the target system for debugging, the IE system performs emulation so as to
operate as the actual target device would operate in the target system.
However, some minor differences exist since the operations are performed via the IE system’s emulation.
(1) Signals input to or output from the emulation gate array (
µ
PD7880)
(2)
Signals input to or output from the emulation gate array (
µ
PD7883)
(3)
Signals input or output from the emulation CPU (
µ
PD178F054)
(4)
Signals input or output from the emulation CPU (
µ
PD780009)
(5) Other signals
The IE system’s circuit is used as follows for the signals listed in (1) to (5) above.
(1) Signals input to or output from the emulation gate array (
µµµµ
PD7880)
See
Figure 4-1 Equivalent Circuit 1 of Emulation Circuit.
•
P57 to P50
•
P67 to P60
(2) Signals input to or output from the emulation gate array (
µµµµ
PD7883)
See
Figure 4-2 Equivalent Circuit 2 of Emulation Circuit.
•
P47 to P40
(3) Signals input to or output from the emulation CPU (
µµµµ
PD178F054)
See
Figure 4-3 Equivalent Circuit 3 of Emulation Circuit.
•
P06 to P00
•
P15 to P10
•
P37 to P30
•
P77 to P70
•
P125 to P120
•
P132 to P130
•
EO1, EO0
•
REGCPU, REGOSC
•
J1 to J4 (AMIFC, FMIFC, VCOL, VCOH)
(4) Signals input to or output from the emulation CPU (
µµµµ
PD780009)
See
Figure 4-4 Equivalent Circuit 4 of Emulation Circuit.
•
X1
•
RESET
