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Buffer effective length
In process of transmit a frame, TxDMA will transmit the bytes of effective length of buffer indicated in TDES1 to
MAC controller. Data for a frame can be in multiple different buffers. If TDES0.FS read by DMA controller is 1,
indicating the beginning of a new frame buffer, DMA will mark the first byte transmitted as the beginning of the
frame. If TDES0.LS read by DMA controller is 1, it indicates the last part of the data of current frame. As long as the
frame length is not particularly large, generally a frame will be stored in a buffer, so TDES0.FS and TDES0.LS will
be set at the same time in same descriptor.
In process of receive a frame, the value of the buffer length field of the received frame must be word-aligned. For
word-aligned or non-word-aligned buffer addresses, the receive operation is not the same as the transmit operation.
If the receive buffer address is word-aligned, it is similar to the sending process, and the effective length of the buffer
is determined by the value configured in RDES1; If the receive buffer address is not word-aligned, the effective
length of the buffer shall be the value configured in RDES1 minus the lower 2 bits of the buffer address. Assuming
that the total size of the cache is 1024 bytes, the address of the buffer is 0x2000 0001, and the lower 2 bits of the
address are 01b, then the effective length of the buffer is 1023 bytes, ranging from 0x2000 0001 at the beginning of
the frame to 0x2000 03FF.
When an SOF is received, DMA controller will set RDES0.FS to 1, and when an EOF is received, RDES0.LS will
be set to 1. If the value of the receive buffer length field is configured to be large enough to store a complete frame,
RDES0.FS and RDES0.LS will be set in the same descriptor. The actual received frame length can be obtained
through these bits of RDES0.FL[13:0]. Application can calculate the unused buffer space by subtracting the actual
received frame length from the value of receive buffer length configuration field. RxDMA always uses a new
descriptor to receive the next frame.
TxDMA
25.4.8.3.1
Transmit frame format
IEEE 802.3 stipulates that a complete transmission frame should consist of preamble, SFD, destination address (DA),
source address (SA), QTAG prefix (optional), length/type field (LT), data, PAD padding field (optional) and FCS
composition. Both preamble and SFD are automatically generated by MAC, and application only needs to store the
destination address, source address, length/type, data, and QTAG, padding field and FCS configured as needed. PAD
and FCS can be automatically generated by configuring TDES1.DP and TDES1.DC respectively.
25.4.8.3.2
Transmit frame processing
A frame can be spread across different buffers and also requires multiple descriptors. When TDES1.FS is set, it means
that the buffer pointed to by current descriptor is frame header. When TDES1.LS is set, it means that the buffer
pointed to by current descriptor is the end of the frame. For other descriptors of current frame (descriptors whose
TDES1.LS is 0), TxDMA controller only modifies and clears its TDES0.OWN bit. After transmit the data of last
buffer, DMA will write the transmit status information of the entire frame into TDES0 of the last transmit descriptor
and return. The data is transferred from system memory to TxFIFO, and start transmit data, but the actual data
transmission is determined by MAC according to cut-through (threshold) mode or store-and-forward mode.
25.4.8.3.3
TxDMA descriptor
TxDMA descriptor structure contains four 32-bit words TDES0, TDES1, TDES2 and TDES3. If IEEE 1588
timestamp function is enabled, TDES2 and TDES3 are also used to store the lower 32 bits of timestamp and the upper
