646
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
6
230.4
230.769
9.75
0.16%
230.769
19.5
0.16%
7
460.8
461.538
4.875
0.16%
461.538
9.75
0.16%
8
921.6
923.076
2.4375
0.16%
923.076
4.875
0.16%
9
2250
2250
1
0%
2250
2
0%
10
4500
impossible
impossible
impossible
4500
1
0%
Notes: The lower the clock frequency of the CPU, the lower the error for a particular baud rate.
23.4.5
Receiver’s tolerance clock deviation
Variations due to transmitter errors (including transmitter side oscillator variations), receiver side baud rate rounding
errors, receiver side oscillator variations, variations due to transmission lines (usually due to The inconsistency
between the low-to-high transition timing of the transceiver and the high-to-low transition timing of the transceiver),
these factors will affect the overall clock system variation. Only when the sum of the above four changes is less than
the tolerance of the USART receiver, the USART asynchronous receiver can work normally.
When receiving data normally, the tolerance of the USART receiver depends on the selection of the data bit length
and whether it is generated using a fractional baud rate. The tolerance of the USART receiver is equal to the maximum
tolerable variation.
Table 23-4 when DIV_Decimal = 0. Tolerance of USART receiver
WL bit
NF is an error
NF is don’t care
0
3.75%
4.375%
1
3.41%
3.97%
Table 23-5 when DIV_Decimal != 0. Tolerance of USART receiver
WL bit
NF is an error
NF is don’t care
0
3.33%
3.88%
1
3.03%
3.53%
23.4.6
Parity control
Parity can be enabled by configuring the USART_CTRL1.PCEN bit.
When the parity bit is enabled for transmission, A parity bit is generated, parity check is performed on reception.
Table 23-6 Frame format
WL bit
PCEN bit
USART frame
