Software Introduction
16
SLWU055A – May 2008 – Revised May 2016
Copyright © 2008–2016, Texas Instruments Incorporated
TSW3070EVM: Amplifier Interface to Current Sink DAC - Arbitrary Waveform
Generator Demonstration
Table 3. Software Feature Descriptions (continued)
Control Name
Input/Output
Description
Read All
Input
Reads all registers from the DAC5682Z device. It is rarely necessary to use this as the
registers are read every time a DAC5682Z control changes.
Load Regs
Input
Loads a DAC5682Z register configuration from a text file. Files need to consist of a single
column with the register values in hexadecimal format.
Save Regs
Input
Saves a DAC5682Z register configuration to a text file.
CDCM7005 REGISTER CONFIGURATION BOX
— GENERAL SETTINGS
Output Settings
Input
Switches the display between the CDCM7005 output register settings and advanced register
settings.
CDCM7005
Operation
Input
Select
Buffer Mode
when there is no VCXO installed or the VCXO is enabled. In this case the
CDCM7005 operates as a buffer. Select
PLL Mode
when a VCXO is being used by the
CDCM7005.
— PLL SETTINGS
M & N Selection
Input
When Auto is selected the M and N divider values are calculated automatically based on the
Reference and VCXO frequencies.
Ref. Freq. (MHz)
Input
Frequency of the reference oscillator given to the CDCM7005.
VCXO Freq.
(MHz)
Input
Frequency of the VCXO used.
M Divider
Input/Output
M divider value.
N Divider
Input/Output
N divider value.
FB_MUX
Input/Output
Feedback MUX select.
Phase Shift
Input
Phase shift select.
Output Freq
(MHz)
Output
Output frequency of the CDCM7005 based on the Reference and VCXO frequencies, and M
and N values. If this frequency differs from the VCXO frequency it is displayed in red.
— OUTPUT SETTINGS
Y0-Y4 Dividers
Input
Selects the output dividers of the CDCM7005 outputs.
Y0-Y4 Levels
Input
Selects between CMOS or LVPECL levels of the CDCM7005 outputs.
Y0-Y4 States
Input
Selects the operating state of the CDCM7005 outputs.
— ADVANCED SETTINGS
Advanced
Registers
Input
CDCM7005 advanced registers. See the CDCM7005 datasheet (
) for more
information on these registers.
TSW3100 CONFIGURATION BOX
File Format
Input
Selects between binary and 16-bit signed integer format. If binary is selected the file must
comply with the requirements described on the TSW3100 documentation. If integer format is
selected, the file must consist of a single column for a real signal or two columns for a two-
channel or complex signal.
Column Delimiter
Input
Indicates the column separator used in the two-channel or complex integer input file.
File Browser
Input
Used to browse the input pattern file.
Output Level
Input
Selects between LVDS or CMOS outputs. Only LVDS is available for the DAC5682Z
Data Format
Input
Selects between 2s complement or offset binary format.
IP Address
Input
IP address of the TSW3100 pattern generator.
TSW3100 State
Input
Selects between Master or Slave mode. The default state is Master mode. See the TSW3100
documentation for more information.
Load and Start
Input
Select this to load a pattern file and start the TSW3100.
Stop Pattern
Input
Select this to stop the pattern.
Re-start Pattern
Input
Select this to re-start the pattern. A loaded must be loaded in memory for this to work.
Command
Output
Shows a list of the commands sent to the TSW3100.
Status
Output
Status of the TSW3100 transaction.
Bytes loaded
Output
Displays the number of bytes loaded to the TSW3100.
