Software Introduction
15
SLWU055A – May 2008 – Revised May 2016
Copyright © 2008–2016, Texas Instruments Incorporated
TSW3070EVM: Amplifier Interface to Current Sink DAC - Arbitrary Waveform
Generator Demonstration
Table 3. Software Feature Descriptions (continued)
Control Name
Input/Output
Description
digital delay
Input/Output
DAC data delay adjustment (0–3 periods of the DAC clock). This can be used to adjust system
level output timing. The same delay is applied to both DACA and DACB data paths.
clock delay
Input/Output
Changes the number of buffers that the input clock goes through. This allows some adjustment
of the setup/hold of the handoff between the receivers and the digital section.
— DAC SETTINGS
DAC mode
Input/Output
Selects between dual DAC mode and single DAC mode. It is also used to select input
interleaved data (dual DAC mode).
DACA Sleep
Input/Output
When set, DACA is put into sleep mode.
DACB Sleep
Input/Output
When set, DACB is put into sleep mode. DACB is not automatically set into sleep mode when
configured for single DAC mode. Set this control in single DAC mode to get the lowest power
configuration since the output is on DACA only.
DACA Gain
Input/Output
Scales the DACA output current in 16 equal steps.
DACB Gain
Input/Output
Scales the DACB output current in 16 equal steps.
Offset
Input/Output
When enabled, the Offset A and Offset B values are summed into the DACA and DACB data
paths. This provides a system-level offset adjustment capability that is independent of the input
data.
offset sync
Input/Output
Transfers the Offset A and Offset B values to the registers used in the DACA and DACB offset
calculations. This control is enabled automatically every time there is a change in the Offset A
or Offset B values.
Offset A
Input/Output
Offset adjustment value for the A data path.
Offset B
Input/Output
Offset adjustment value for the B data path.
DAC A LPF
Input/Output
Enables a 95-kHz low-pass filter corner on the DACA current source bias. When disabled a
472-Hz filter corner is used.
DAC B LPF
Input/Output
Enables a 95-kHz low-pass filter corner on the DACB current source bias. When disabled a
472-Hz filter corner is used.
— ERROR SETTINGS
SLFST Error
Input/Output
Masks out SLFTST Errors
FIFO Error
Input/Output
Masks out FIFO Errors
Setup/Hold Error
Input/Output
Masks out Setup/Hold Errors.
SLFST error reset
Input/Output
Asserted when the Digital Self Test (SLFTST) fails. Clear to reset a SLFST error.
FIFO error reset
Input/Output
Asserted when the FIFO pointers overrun each other causing a sample to be missed. Clear to
reset a FIFO error.
Setup/Hold error
reset
Input/Output
Any received data pattern other than 0xAAAA or 0x5555 causes this bit to be set. Clear to
reset a Setup/Hold error.
SDO
Input/Output
Selects the output signal on the SDO pin.
— SYNC SETTINGS
Serial interface
Input/Output
Selects between 3 pin or 4 pin serial interface mode.
sync source
Input/Output
Selects the synchronization signal source. If soft sync is selected the software sync control is
used as the only synchronization input and the LVDS external SYNC input pins are ignored.
software sync
Input/Output
This control can be used as a substitute for the LVDS external SYNC input pins for both
synchronization and transmit enable control.
hold sync
Input/Output
Enables the sync to the FIFO output HOLD block.
clk div sync
Input/Output
Enables the clock divider sync.
FIFO sync
Input/Output
Enables the FIFO offset sync.
self test
Input/Output
Enables a Digital Self Test (SLFTST) of the core logic
FA002
Input/Output
Keep disabled. Used only for factory test purposes.
Fuse A
Input/Output
Keep disabled. Used only for factory test purposes.
Fuse B
Input/Output
Keep disabled. Used only for factory test purposes.
ATEST
Input/Output
Keep disabled. Used only for factory test purposes.
— SEND/SAVE SETTINGS
Send All
Input
Writes all registers to the DAC5682Z device.
