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Free-Running VCO Noise (Internal Divide by 2 Enabled) 

Fout = 634 MHz (1268 MHz/2) 

Fout = 657 MHz (1314 MHz/2) 

Fout = 680 MHz (1360 MHz/2) 

The plots to the left show the 

true phase noise capability of 

the VCO.  In order to take 

these plots, the E5052 phase 

noise analyzer was used. 

 

 

The method was to lock the 

PLL to the proper frequency, 

then disable the EN_PLL, 

EN_PLLLDO1, and 

EN_PLLLDO2 bits.  The 

equipment needs to be able to 

track the VCO phase noise to 

measure in this way, and one 

can not let the VCO drift too 

far off in frequency.  If this kind 

of equipment is not available, 

the VCO phase noise can also 

be measured by making a 

very narrow loop bandwidth 

filter.   

 

When divide by 2 is enabled, 

the phase noise at lower 

offsets is about 6 dB better.  At 

high offsets, the overall phase 

noise improvement may be 

lower because the divider is 

noise floor is adding to the 

phase noise. 

 

 

 

 

 

7

Summary of Contents for LMX2531LQ1312E

Page 1: ...2531LQ1312E Evaluation Board Operating Instructions National Semiconductor Corporation Timing Devices Business Group 10333 North Meridian Suite 400 Indianapolis IN 46290 LMX2531LQ1312EFPEB Rev 4 02 20...

Page 2: ...DIVIDE BY 2 DISABLED 6 FREE RUNNING VCO NOISE INTERNAL DIVIDE BY 2 ENABLED 7 FRACTIONAL SPURS INTERNAL DIVIDE BY 2 DISABLED 8 FRACTIONAL SPURS INTERNAL DIVIDE BY 2 ENABLED 9 INTEGER SPURS INTERNAL DIV...

Page 3: ...s tend to be very noisy and should be used with caution If a signal generator is used the signal generator phase noise contribution can be reduced by setting the signal to 80 MHz and dividing this dow...

Page 4: ...or If a signal generator is used the RF should be set to ON If using the lower frequency band DIV2 1 understand that the VCO frequency in CodeLoader should be twice the frequency at the Fout pin Ensur...

Page 5: ...3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Phase Noise Output Frequency 1314 MHz Internal Divide by 2 Disabled DIV2 0 Output Frequency 657 MHz Internal Divide by...

Page 6: ...e EN_PLL EN_PLLLDO1 and EN_PLLLDO2 bits The equipment needs to be able to track the VCO phase noise to measure in this way and one can not let the VCO drift too far off in frequency If this kind of eq...

Page 7: ...o lock the PLL to the proper frequency then disable the EN_PLL EN_PLLLDO1 and EN_PLLLDO2 bits The equipment needs to be able to track the VCO phase noise to measure in this way and one can not let the...

Page 8: ...pur at 250 kHz offset at a worst case frequency of 1270 25 MHz is 74 4 dBc Worst case channels occur at exactly one channel spacing above or below a multiple of the crystal frequency Fractional Spur a...

Page 9: ...c Since this mode uses the divide by 2 mode the channel spacing here is actually 125 kHz If there was a fractional spur at 125 kHz it could be eliminated by doubling the channel spacing before the div...

Page 10: ...T R U C T I O N S Integer Spurs Internal Divide by 2 Enabled Spur at 10 MHz offset for a frequency of 1268 MHz is 92 8 dBc Spur at 10 MHz offset for a frequency of 1314 MHz is below the spectrum anal...

Page 11: ...rs Internal Divide by 2 Enabled Spur at 10 MHz offset for a frequency of 634 MHz is below the spectrum analyzer noise floor Spur at 10 MHz offset for a frequency of 657 MHz is below the spectrum analy...

Page 12: ...A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader Settings The CodeLoader program is designed to work with many devices When CodeLoader is first started it is necessary t...

Page 13: ...enu This restores bit settings and frequencies but not the Port Setup information The default reference oscillator used for these instructions was 10 MHz but there is an alternate mode for a 61 44 MHz...

Page 14: ...bit to view more information about what this does When the DIV2 bit is enabled the frequency from the part will be half of that shown on the PLL VCO tab The frequency on the PLL VCO tab does not refl...

Page 15: ...S The Registers tab shows the literal bits that are being sent to the part These are the registers every time the PLL is loaded by using the menu command or trl L R5 INIT1 and R5 INIT 2 are just the...

Page 16: ...T R U C T I O N S The port setup tells CodeLoader what information goes where If this is wrong the part will not program Although LPT1 is usually correct CodeLoader does NOT automatically detect the...

Page 17: ...10 uWIRE R10 C6 R2pLF C16 FRAME Fout Vcc R21 R19 R20 C1 R2 C12 C2 VccVCO VccDIG VccPLL VccBUF R3 C3 C17 R4 C9 C4 R5 C5 OSCin VccVCO VccPLL VccBUF C13 C18 C20 R7 R23 R22 Ftest LD C15 C22 R1 R9 TRIGGE...

Page 18: ...9 2 Panasonic P 22AHCT ND 603 10 0 1W Thick Film 0 22 R22 R23 10 2 Vishay CRCW06033R3JRT1 603 0 1W Thick Film 3 3 R1 R18 5 11 4 Vishay CRCW0603100JRT1 603 5 0 1W Thick Film 10 R2 R3 R4 R5 12 1 Vishay...

Page 19: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Top Layer 19...

Page 20: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 1 Groun 5 Mils Down FR4 d Plane 1 20...

Page 21: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 2 Power 21...

Page 22: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bottom Layer Signal Note Total Board Thickness 61 mils 22...

Page 23: ...L M X 2 5 3 1 L Q 1 3 1 2 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Top Build Diagram 23...

Page 24: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

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