1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Title
Number
Revision
Size
B
Date:
11/3/2009
Sheet of
File:
C:\Projects\..\LMH1981.SchDoc
Drawn By:
J1
Ref. In
VCC
HSYNC_B
VSYNC_A
1
1
2
2
3
3
4
4
8
8
7
7
6
6
5
5
J2
EXT HVF IN
GND
HSYNC_A
10.0k 1%
R1
BPOUT
13
Video In
4
VFOUT
9
GND
5
VSOUT
8
CSOUT
12
VCC
11
GND
2
VCC
6
VCC
3
Rext
1
HSOUT
7
GND
10
OEOUT
14
U1
LMH1981MT
TP2
VCC
FSYNC_A
VSYNC_B
FSYNC_B
INIT
1
2
JP1
75R TERM
1
2
JP2
LPF ENAB
TP1
VIDEO IN
VC
1
OUT
4
G
N
D
3
E
N
2
V
C
C
6
X1
ASVV-27.000MHZ-N152-T
TP3
Vtune
R20
5K
1
2
JP5
XO DISAB
HSYNC_A
HSYNC_B
HIN
VIN
VSYNC_A
FIN
FSYNC_A
HSYNC_B
VSYNC_B
FSYNC_B
Layout Note: JP Legend is
"Short = LMH1981"
"Open = 27M/EXT HVF"
Layout Note: Place U4 on
bottom side of PCB, and
do not label IC.
Layout Note:
Pot Legend is
"VCXO TUNE"
Note:
Short = Enable
Open = Hi-Z
1
2
JP3
INPUT SEL
1
2
JP4
MUX ENAB
Layout Note:
XO Legend is
"27 MHz VCXO Source"
Layout Note: IC Legend is
"LMH1981 Sync Separator"
OSCin
3V3
3V3
3V3
OPEN
R18
Analog Input and LMH1981 Sync Separator
External HVF+INIT Input Header
27 MHz Clock Source from VCXO or SMA Input
Quad SPDT Input MUX with Output Hi-Z
Layout Note: Pin Legend is
"EXT INIT" (inline w/ pin 8)
"EXT F " (inline w/ pin 7)
"EXT V" (inline w/ pin 6)
"EXT H" (inline w/ pin 5)
"GND" (inline w/ pins 1-4)
75.0
R4
33
R2
33
R5
33
R6
33
R10
33
R13
OPEN
R15
33
R8
33
R19
OPEN
R21
0.1uF
C2
0.1uF
C8
0.1uF
C3
0.1uF
C14
0.1uF
C10
560pF
C9
C0G/NP0: 0.1uF
C18
10uF
C6
10uF
C13
10uF
C17
10.0k
R7
10.0k
R9
IN
1
NC1
2
NO1
3
COM1
4
NC2
5
NO2
6
COM2
7
GND
8
V+
16
EN
15
NC4
14
NO4
13
COM4
12
NC3
11
NO3
10
COM3
9
U2
TS3A5018PW
250mA
220 ohm
L1
250mA
220 ohm
L2
250mA
220 ohm
L3
FIN
VIN
HIN
OPEN
R23
OPEN
R22
3V3
0.1uF
C19
Note: 27 MHz Clock Source can come from
either the on-board VCXO or the SMA Input.
If the SMA Input is used, the VCXO output
should be disabled. The SMA input signal
can be AC or DC coupled, and terminated
and.or biased as needed using the available
resistor options.
Layout Note: Minimize
stub length of the traces
on 27M net.
OPEN
R12
OPEN
R11
OPEN
R14
Layout Note: Minimize stub
length of HSYNC_B
INIT
27M
OPEN
R16
OPEN
R17
Note: If U4 is not populated,
shorts can be installed to
directly connect the HVF
signals to the LMH1983 inputs.
3V3
50-OHM CONTROLLED IMPEDANCE
1uF
C15
1uF
C16
1uF
C12
1uF
C11
1uF
C4
1uF
C5
0
R3
VCC
VCC
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
TP4
GND
Layout Note: Distribute GND test
points around the PCB.
TP5
GND
TP6
GND
TP7
GND
TP8
GND
TP9
GND
TP10
GND
TP11
GND
1
2
4
3
SW1
FSM2JSMA
1uF
C1
OPEN
C7
1
2
3
4
5
J3
27MHz SMA In
LMH1983 Eval Board - LMH1981
B
Sauerwald
4 5