1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Title
Number
Revision
Size
C
Date:
11/3/2009
Sheet of
File:
C:\Projects\..\LMH1983 Demo Board.SchDoc
Drawn By:
3V3
VDD_XO
1
0
0
O
HM
D
IF
F
.
IM
PED
A
N
C
E
VDD_XO
LMH1983 Evaluation Board
10uF
C44
0
R51
0
R53
4.75k
R39
4.75k
R41
1
2
JP12
TP18
F_IN
TP17
V_IN
TP16
H_IN
TP20
ADDR
TP29
VC_BUF
OPEN
C40
TP19
INIT
1
2
3
JP9
I2C ADDR SEL
3V3
Fout1
Fout2
Fout3
Layout Note: JP Legend is
"Disable XO"
3V3
TP28
VDD_XO
Layout Note: XO Legend is
"27MHz VCXO"
Layout Note: TP Legend is
"VDD_XO"
Layout Note:
Pin legend is:
"65h = Pin 1-2"
"66h = Float Pin 2"
"67h = Pin 2-3"
VDD
Layout Note:
TP Legend is
"XO_CLK"
HIN
VIN
FIN
INIT
OPEN
R33
OPEN
R30
OPEN
R34
OPEN
R31
OPEN
R32
0.1uF
C32
33
R38
33
R42
33
R40
33
R26
NOALIGN
NOREF
NOLOCK
0.1uF
C25
0.1uF
C23
0.1uF
C21
33
R24
0.01uF
C43
0.1uF
C42
OPEN
C47
0.1uF
C46
250mA
220 ohm
L4
VC
1
OUT
4
G
N
D
3
EN
2
V
C
C
6
OUTA
5
X2
357LB3I027M0000
OPEN
R37
49.9
R55
OPEN
R54
0.1uF
C48
CLKout1_P
CLKout1_N
TP26
XOclk+
CLKout4_P
CLKout4_N
OPEN
R36
Note: XOin pair can be driven by a VCXO with LVCMOS clock
or LVDS clock.
-LVCMOS (default):
XOin+: Connect to VCXO's single-ended output.
XOin-: Bias to 1.65VDC via 1.00k divider resistors using the
VCXO's supply (VDD_XO) and local ground for optimal CMR.
OUTA (VCXO pin 5): No connect (N/C)
-LVDS:
XOin+/-: Connect to VCXO's LVDS output and terminated with
100R differential.
OUTA: Complementary LVDS output pin. Remove 1k resistors
and 0.1uF cap and install series resistor.
XOin_P
XOin_N
X
O
in_P
X
O
in_N
4
1
2
3
JP11
I2C CONN
Layout Note: Place JP3
near edge of PCB.
Pin Legend is:
"GND" (pin 1)
"N/C" (pin 2)
"SCL" (pin 3)
"SDA" (pin 4)
NOLOCK
NOALIGN
NOREF
Rev. 1
TP12
Fout4
0
R44
1uF
C20
1uF
C22
1uF
C24
VDD
1uF
C45
1uF
C41
33
R43
33
R45
OPEN
C38
OPEN
C37
OPEN
C36
TP23
NO_LOCK
TP24
NO_ALIGN
TP25
NO_REF
OPEN
C30
OSCin
Fout4
33
R27
TP13
Fout3
OPEN
C29
33
R25
TP14
Fout2
OPEN
C27
TP15
Fout1
OPEN
C26
47uF
C39
OPEN
R49
TP21
SDA
TP22
SCL
OPEN
R28
Layout Note: Pin Legend is
"Fout1" (inline w/ JP11.2)
"Fout2" (inline w/ JP12.2)
"Fout3" (inline w/ JP13.2)
"Fout4" (inline w/ JP14.2)
"GND" (inline w/ pin 1 of JP11, JP12, JP13, JP14)
OPEN
C31
OPEN
C28
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
PLL1 Loop Filter and VCXO
TP27
VC
OPEN
C34
OPEN
C35
G
N
D
18
G
N
D
21
G
N
D
39
D
A
P
V
D
D
_P
LL1
1
V
D
D
_I
O
2
V
D
D
_I
O
10
V
D
D
_C
LK
4
16
V
D
D
_P
LL34
19
V
D
D
_C
LK
3
20
V
D
D
_C
LK
2
31
V
D
D
_P
LL2
32
V
D
D
_C
LK
1
38
36
CLKout1-
35
Fout1
37
28
CLKout2-
29
Fout2
30
Fout3
22
23
CLKout3-
24
CLKout4-
14
15
Fout4/OSCin
17
Hin
3
Vin
4
Fin
5
INIT
6
ADDR
7
SDA
8
SCL
9
NO_LOCK
11
NO_ALIGN
12
NO_REF
13
C
b
yp3
25
C
b
yp4
26
C
b
yp2
27
XOin-
33
XOin+
34
VC_LPF
40
U3
LMH1983SQ
OPEN
R29
OPEN
R35
OPEN
R46
CLKout2_N
CLKout2_P
CLKout3_N
CLKout3_P
CLKout1_P
CLKout1_N
CLKout2_N
CLKout3_N
CLKout4_N
CLKout4_P
CLKout3_P
CLKout2_P
VDD_PLL1
VDD_PLL2
VDD_PLL34
VDD_CLK4
VDD_CLK3
VDD_CLK2
VDD_CLK1
Layout Note: Pin 17 is a programmable I/O pin.
When the pin is an output, the resistor should be
populated for net "Fout4" (default). When the pin
is an input, the other resistor should be populated
for net "OSCin". Minimize trace stubs on this
pin.
4
3
2
1
6
5
V
+
V
-
U4
LMP7711MK
1uF
C33
Fout1
Fout2
Fout3
Fout4
10.0k
R48
OPEN
R50
VDD_XO
Layout Note: On Fout* pins and pins 11, 12, 13,
place direct components as close to LMH1983 as
possible.
1
2
JP6
1
2
JP7
1
2
JP8
1
2
JP10
3.0k
R52
1.82k
R56
17.4k
R47
SDA
SCL
LMH1983 Eval Board - LMH1983
B
Sauerwald
4 5
