National Semiconductor LM64, User Manual

Page: 8 / 11

8
8
4.0 Schematic of the LM64 Evaluation Board
C2
0.1uF
+ 3.3 VDC
R3 22
R5 1.5K
U3
AT24C02-10SI-2.7
1
2
3
4
8
7
6
5
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
A0
R2
1M
GPIO3
C14
0.1uF
SDA
U2
CY7C64603-52NC
17 4 15 16
2
1
3
14
10
11
5 29
21 8
6 7 30 31 32 33 34
35
36
43
44
45
46
48
49
50
51
25
24
18
9
12
28
27
39 47 52
40
42
41
37
38 22 23
19 20
13 26
R
E
S
E
R
V
E
D
_3
W
A
K
E
U
P
#
R
E
S
E
R
V
E
D
_2
X
C
LK
S
E
L
SCL
V
cc
1
SDA
V
cc
2
PA4/FWR#
PA5/FRD#
A
V
cc
P
B
0/
T2
G
nd
2
A
G
nd
X
IN
X
O
U
T
P
B
1/
T2
E
X
P
B
2/
R
X
D
1
P
B
3/
TX
D
1
P
B
4/
IN
T4
P
B
5/
IN
T5
#
PB6/INT6
PB7/T2OUT
PC0/RxD0
PC1/TxD0
PC2/INT0#
PC3/INT1#
PC4/T0
PC5/T1
PC6/WR#
PC7/RD#
USBD+
USBD-
DISCON#
R
E
S
E
R
V
E
D
_1
CLKOUT
RESET#
V
cc
3
G
nd
4
G
nd
5
G
nd
6
V
cc
4
R
D
Y
2/
A
O
E
CTL0/AINFLAG
CTL2/AOUTFLAG
X
C
LK
R
E
S
E
R
V
E
D
_4
R
E
S
E
R
V
E
D
_5
R
E
S
E
R
V
E
D
_6
R
E
S
E
R
V
E
D
_7
G
nd
1
G
nd
3
C1
0.1uF
PWM
R8
1.5K
R7
1.5K
C4
0.1uF
Alert#
J1
USB-B
1
2
3
4
5
6
VBUS
D-
D+
GND
SHELL_1
SHELL_2
Use a 0.1 uF capacitor for each
Vcc pin of U2 and Reserved_6 pin.
GND
U1
LP2950CDT-3.3/TO252
1 3
IN OUT
C11
2.2uF
GPIO4
L1
Tach In
C6
0.1uF
C10
0.1uF
SCL
C12
0.1uF
PWM (Page 2)
C5
0.1uF
Tach In
GPIO1
C9
2.2uF
SDA
R1
100k
Y1
12 MHz
C8
33pF
TACH IN (Page 2)
GPIO5
R6
1M
SCL
C7
33pF
TCRIT
R4 22
PWM
C3
0.1uF
+ 3.3 VDC
GPIO2
SCL
SDA
1 uH
C13
0.1uF
+ 3.3 VDC
Figure 5a. LM64 Evaluation Board Schematic, Page 1 of 2