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ADC12V170 Evaluation Board User’s Guide 

N

 

- 5 -  

www.national.com 

Rev 0.0

 

 

 

Figure 2.  Analog Input Network of ADC12V170LFEB:  F

IN

 < 150 MHz 

 

 

 

Figure 3.  Analog Input Network of ADC12V170HFEB:  F

IN

 > 150 MHz 

 
 

 

4.3 ADC Reference and Input Common Mode 

The internal 1.0V reference on the ADC12V170 is used 
to  acquire  all  of  the  results  in  the  ADC12V170 
datasheet.    It  is  recommended  to  use  the  internal 
reference on the ADC12V170.  However, if an external 
reference  is  required,  the  ADC12V170  is  capable  of 
accepting  an  external  reference  voltage  between  0.9V 
and  1.1V  (1.0V recommended).  The input impedance 
of  the  ADC12V170  V

REF

  pin  (pin  46)  is  9  k

.  

Therefore,  to  overdrive  this  pin,  the  output  impedance 
of the exernal reference source should be << 9 k

It  is  recommended  to  use  the  voltage  at  the  V

RM

    pin 

(pin  45)  of  the  ADC12V170  to  provide  the  1.5V 
common  mode  voltage  required  for  the  differential 
analog  inputs  V

IN+

  and  V

IN-

.    The  ADC12V170 

evaluation  board  is  factory-assembled  with  V

RM

 

connected  to  the  transformer  center-tap  through  a 

49.9

 resistor to provide the necessary common mode 

voltage to the differential analog input.   

4.4 Board Outputs 

The  digitized  12-bit  output  word  from  the  ADC12V170 
evaluation  board  is  presented  in  interleaved  double 
data  rate  (DDR)  format.    The  digital  output  lines  from 
the  ADC12V170  evaluation  board  consist  of  16  lines 
which  are  arranged  into  8  LVDS  pairs.    These  8  pairs 
of lines carry the 12-bit output data (6 pairs), the DRDY 
signal which should be used to capture the output data 
(1  pair)  and  the  over-range  bit  (OVR)  which  indicates 
that  the  digital  output  has  exceeded  the  maximum 
digitizable signal (1 pair). 

Since  the  data  is presented in interleaved double data 
rate (DDR) format, the 12-bit word is output on 6 data 
pair  lines  with  half  of  the  data  (odd  bits:  D1+/-,  D3+/-, 

Summary of Contents for ADC12V170

Page 1: ...N www national com Rev 0 0 October 2007 Evaluation Board User s Guide for ADC12V170 12 Bit 170 MSPS Analog to Digital Converter with LVDS Outputs ...

Page 2: ... 0 0 Figure 1 ADC12V170 Evaluation Board Connector and Jumper Locations Analog Input FIN 150 MHz Single Ended Clock Input 5 0V Power Connector ADC CLK_SEL DF Jumper PD Jumper Clock Buffer Reverse Side Analog Input Network Analog Input FIN 150 MHz FutureBus Connector ...

Page 3: ...quencies greater than 150 MHz 2 ADC12V170LFEB low frequency version for input frequencies less than 150 MHz Please refer to the input circuit configurations described in the Analog Input Section 4 2 of this guide The location and description of the components on the ADC12V170 evaluation board can be found in Figure 1 as well as Section 5 0 Schematic and Section 7 0 Bill of Materials of this user s...

Page 4: ...urther improve the noise performance of the ADC by filtering out the broadband noise of the clock source All results in the ADC12V170 datasheet are obtained with a tunable bandpass filter made by Trilithic Inc in the clock signal path The noise performance of the ADC12V170 can be improved further by making the edge transitions of the clock signal entering the ADC clock input pin 11 CLK very sharp ...

Page 5: ...the ADC12V170 to provide the 1 5V common mode voltage required for the differential analog inputs VIN and VIN The ADC12V170 evaluation board is factory assembled with VRM connected to the transformer center tap through a 49 9Ω resistor to provide the necessary common mode voltage to the differential analog input 4 4 Board Outputs The digitized 12 bit output word from the ADC12V170 evaluation board...

Page 6: ... the first half of the clock period and these lines will carry bit D10 during the second half of the clock period Similarly pins A10 B10 will carry D1 during the first half of the clock period and these pins will carry D0 during the second half of the clock period The DRDY signal which is used to capture the data is also in LVDS format and it is available at pins A4 D4 DRDY on the FutureBus connec...

Page 7: ...ADC12V170 Evaluation Board User s Guide N 7 www national com Rev 0 0 5 0 Evaluation Board Schematic Figure 4 Signals ...

Page 8: ...ADC12V170 Evaluation Board User s Guide N 8 www national com Rev 0 0 5 0 Schematic cont Figure 5 Power Distribution ...

Page 9: ...ADC12V170 Evaluation Board User s Guide N 9 www national com Rev 0 0 6 0 Evaluation Board Layout Figure 6 Layer 1 Signal ...

Page 10: ...ADC12V170 Evaluation Board User s Guide N 10 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 7 Layer 2 Ground ...

Page 11: ...ADC12V170 Evaluation Board User s Guide N 11 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 8 Layer 3 Power ...

Page 12: ...ADC12V170 Evaluation Board User s Guide N 12 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 9 Layer 4 Signal ...

Page 13: ...c_7343 Kemet 15 2 L1 L2 Ferrite Bead Core SMD FERRITE BEAD CORE 4 5X3 2X1 8 Panasonic ECG 16 1 JTAG Jumper 1x8 JUMPER BLOCK USING 8 PIN SIP HEADER Samtec 17 1 PD Jumper 2X2 2X2 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 18 1 CLK_SEL DF Jumper 2X4 2X4 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 19 1 Shunt PLACE SHUNT ACROSS PINS 7 8 ON CLK_SEL DF JUMPER FCI Electronic 20 1 U1...

Page 14: ...ANTALUM 6 3V 10 sm c_7343 Kemet 15 2 L1 L2 Ferrite Bead Core SMD FERRITE BEAD CORE 4 5X3 2X1 8 Panasonic ECG 16 1 JTAG Jumper 1x8 JUMPER BLOCK USING 8 PIN SIP HEADER Samtec 17 1 PD Jumper 2X2 2X2 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 18 1 CLK_SEL DF Jumper 2X4 2X4 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 19 1 Shunt PLACE SHUNT ACROSS PINS 7 8 ON CLK_SEL DF JUMPER FCI...

Page 15: ...tain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its sa...

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