5
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ADC
Input
10pF
V
CMO
0.1uF
0.1uF
V
IN
0.1uF
25
Ω
25
Ω
MABACT0039
0.1uF
0.1uF
MABACT0039
Figure 3. Analog Input Network for F
IN
> 70MHz
For input frequencies below 70MHz the circuit of
Figure 4
may be used.
ADC
Input
18 pF
V
CMO
0.1
µ
F
0.1
µ
F
V
IN
ADT1-1WT
50
Ω
0.1
µ
F
20
Ω
20
Ω
Figure 4. Analog Input Network for F
IN
< 70MHz
4.2 ADC reference circuitry
The ADC14DC105 can use an internal or external 1.2V
reference. This Evaluation Board is configured to use the
internal reference.
4.3 ADC clock circuit
Solder jumpers are used to select the path of the clock to
the ADC. While not as convenient as pin-type jumpers,
these introduce less noise into the clock signal.
Care must be taken to provide a high quality low jitter
clock source. The board has a Pletronics SM7745 type
crystal clock. It is buffered by U11 (NC7WV125) and
applied to the ADC’s clock input pin.
The user can configure the board for an external clock at
connector J1. For this option short the pins of solder
jumper JP4 and open the pins of JP10. It may also be
necessary to remove L5 so the crystal is not powered.
Refer to the schematic for more detail.
4.4 Digital Data Output
The digital output data for Channel A is available at pins
B4 (MSB) through B17 of the WaveVision™ (WV4)
connector J8. The digital output data for Channel B is
available at pins A4 (MSB) through A17 of the
WaveVision™ (WV4) connector J8.
4.5 Data Format/ Duty Cycle Stabilizer
Output data format and the duty cycle stabilizer (DCS)
are controlled by jumper JP17.
Shorting pins 1-2 of JP17 sets the output format to 2’s
complement with DCS Off.
Shorting pins 3-4 of JP17sets the output format to 2’s
complement with DCS On.
Shorting pins 5-6 of JP17 sets the output format to offset
binary with DCS On.
Shorting pins 7-8 of JP17 sets the output format to offset
binary with DCS Off. This is the default setting.
4.6 Power Supply Connections
Power to this board is supplied through power connector
JR1. The only supply needed is +5V at pin 2 plus ground
at pin 1.
Voltage and current requirements for the ADC14DC105
Evaluation Board are:
•
+5.0V at 500 mA
5.0 Installing the ADC14DC105 Evaluation Board
The evaluation board requires a single power supply as
described in
Section 4.6
.
NOTE: power to the
WaveVision4 Data Capture Board should be applied
before the power to the ADC14DC105 Evaluation
Board to insure that the FPGA on the WaveVison5
Data Capture Board is not damaged.
An appropriate
signal source should be connected to the Signal Input
SMA connector J9 (Channel A) or J5 (Channel B). When
evaluating dynamic performance, an appropriate signal
generator (such as the HP8644B or the R&S SME-03)
with 50 Ohm source impedance should be connected to
the Analog Input connector through an appropriate
bandpass filter as even the best signal generator
available can not produce a signal pure enough to
evaluate the dynamic performance of an ADC.
If this board is used in conjunction with the the
WaveVision5™ Data Capture Board and WaveVision5™
software, a USB cable must be connected between the
Data Capture Board and the host. See the
WaveVision5™ Data Capture Board manual for details.
