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http://www.national.com

 

1.0 Introduction 

The ADC10080EVAL Design Kit (consisting of the Evaluation Board 
and this manual) is designed to ease evaluation and design-in of 
National's ADC10040, ADC10065, or ADC10080 10-bit Analog-to-
Digital Converters, which operate at speeds up to 40, 65, and 80 
MSPS. Further reference in this manual to the ADC10080 is meant 
to also include the ADC10040 and the ADC10065 unless otherwise 
specified. The latest datasheet for these products can be obtained 
from http://www.national.com. 

The evaluation board can be used in either of two modes. In the 
Manual mode, suitable test equipment, such as a logic analyzer, 
can be used with the board to evaluate the ADC10080 performance. 
In the Computer mode, evaluation is simplified by connecting the 
board to the WaveVision™ Digital Interface Board (order number 
WAVEVSN BRD 4.0). It is connected to a personal computer 
through a USB port and running WaveVision™ software, operating 
under Microsoft Windows 95 or later. The WaveVision™ software 
can perform an FFT on the captured data upon command and, with 
the frequency domain plot, shows dynamic performance in the form 
of SNR, SINAD, THD and SFDR. 

The signal at J1, the Analog Input to the board, is digitized and is 
available at pins B4 through B13 of J2 and pins 10 through 19 of 
JP4. See the board schematic for more details. 

 

2.0 Quick Start 

Refer to the board layout for locations of test points and major 
components.  

For Stand-Alone operation: 

1. 

Select  the input voltage range by inserting a jumper into JP1. 
Set the jumper on pins 1&2 for 2.0 Vpp. Set the jumper on pins 
2&3 for 1.5 Vpp. If no jumper is inserted, 1.0 Vpp is assumed. 

2. 

To make the ADC10080 active, insure there is no jumper on 
JP3. 

3. 

Select the output data format using JP2. When the jumper is 
on pins 1&2, 2’s complement data format is selected. If the 
jumper is on pins 2&3, offset binary is selected. 

4. 

Connect a clean power supply to Power Connector JS1. Refer 
to Table 1 for power supply description and requirements. 

5. 

Connect a signal of the selected amplitude (see step 1) from a 
50-Ohm source to Analog Input BNC J1. Insure that the signal 
is not over-ranged, by examining a histogram. (Either by using 
WaveVision

tm

, or the logic analyzer being used.) Over-range 

signals will dramatically increase the THD. 

6. 

The digitized signal is available at pins B4 through B13 of J2 
and pins 10 through 19 of JP4. 

 

 

JS1 pin  

number 

Description Voltage 

Range 

Vcc for Crystal and 

VDDA for 

ADC10080 

2.7 - 3.3 V 

2 Ground  0V 

VDDIO 

2.5 – 3.3 V 

Output Buffer VCC 

4.9 – 5.1 V 

 

 

Table 1 

 

 

 

 

For Computer mode operation: 

1.  Connect the evaluation board to the WaveVision

tm

 Digital 

Interface Board. See the instruction manual supplied with the 
WaveVision

tm

 kit. The latest WaveVision

tm

 software can be 

obtained from http://www.national.com. 

2. 

Select  the input voltage range by inserting a jumper into JP1. 
Set the jumper on pins 1&2 for 2.0 Vpp. Set the jumper on pins 
2&3 for 1.5 Vpp. If no jumper is inserted, 1.0 Vpp is assumed. 

3. 

To make the ADC10080 active, insure there is no jumper on 
JP3. 

4. 

Select pins 2&3 on JP2 so that the output data is offset binary. 

5. 

Connect a clean power supply to Power Connector JS1. Refer 
to Table 1 for power supply description and requirements. 

6.  If the output level goes over range as seen on the data 

captured through WaveVision™, reduce the output level from 
the signal generator and capture data again. If the output level 
does not reach codes of 25 and 1000, increase the output level 
from the signal generator and capture data again. 

 

3.0 Functional Description 

The ADC10080 Evaluation Board schematic is shown in 

Section 5

3.1 The Signal Input 

The signal transformer T1 provides single-ended to differential 
conversion. The common mode voltage VCOM provided by the 
chip, sets the common mode of the input signal by biasing the 
center tap of T1. 

The differential signal present on the secondary side of the 
transformer is then sent through a low pass filter set up by R1, R5 & 
C9.  

It is important when evaluating the dynamic performance of the 
ADC10080 (or any A/D converter), that a clean sine wave be 
presented to the converter. To do this it is necessary to use a 
bandpass or a low pass filter between the signal source and the 
ADC10080 evaluation board input J1. Even the best signal 
generators available do not provide adequate noise and distortion 
performance for proper evaluation of a 10-bit ADC. A high-quality 
bandpass filter with better than 12-bit equivalent noise 
characteristics and at least 80dB stop band attenuation is ideal. No 
scope or other test equipment should be connected to any input 
circuitry while gathering data. 

3.2 Digital Data Output. 

The digital output data from the ADC10080 is available at the 96-pin 
Euro connector J2 and header JP4. Series resistors R7 – R17 
provide data line dampening that may occur with long cables. U3 
provides buffering to drive the cable. U3’s VCC may be adjusted for 
various output levels. Refer to Table 1 for voltage range. 

3.3 ADC10080 Control Pins. 

The ADC10080 has three control pins, making it a very versatile 
converter. They are Standby (Pin 28 – STBY), Data Format (Pin 15 
– DF) and Input Range Select (Pin 5 – IRS). 

3.3.1 The Standby (STBY) Pin 

When this pin is pulled high (pins 1&2 of JP3 are connected), the 
converter is put into ‘standby’ mode. The converter consumes only 
13.5 mW of power. When STBY is tied to VSSA (JP3 is open), the 
ADC is in full operation. 

 
3.3.2  The Data Format (DF) pin 

This pin sets the output data format of the ADC10080. When this 
pin is pulled to VDDA (pins 1&2 of JP2 are connected), the output is 
2’s complement. When pulled down to VSSA (pins 2&3 of JP2 are 
connected), the data  output is offset binary. 

 

 

 

 

Summary of Contents for ADC10040

Page 1: ... May 9 2005 Rev 1 3 Evaluation Board User s Guide ADC10040 10 Bit 40 MSPS 3 Volt 55 5 mW A D Converter ADC10065 10 Bit 65 MSPS 3 Volt 68 5 mW A D Converter ADC10080 10 Bit 80 MSPS 3 Volt 78 6 mW A D Converter 2005 National Semiconductor Corporation ...

Page 2: ...Input 3 3 2 Digital Data Output 3 3 3 ADC10080 Control Pins 3 3 3 1 The Standby STBY Pin 3 3 3 2 The Data Format DF pin 3 3 3 3 The Input Range Select IRS Pin 4 3 3 4 Power Supply Connections 4 4 0 Obtaining Best Results 4 4 1 Clock Timing 4 4 2 Coherent Sampling 4 4 3 FFT Windowing Technique 4 5 0 Hardware Documentation 6 ...

Page 3: ...aveVision tm software can be obtained from http www national com 2 Select the input voltage range by inserting a jumper into JP1 Set the jumper on pins 1 2 for 2 0 Vpp Set the jumper on pins 2 3 for 1 5 Vpp If no jumper is inserted 1 0 Vpp is assumed 3 To make the ADC10080 active insure there is no jumper on JP3 4 Select pins 2 3 on JP2 so that the output data is offset binary 5 Connect a clean po...

Page 4: ...oducing inconsistent results when performing repeated testing The presence of these artifacts means that the ADC under test may perform better than the measurements would indicate We can eliminate the need for windowing and get more consistent results if we observe the proper ratios between the input and sampling frequencies This greatly increases the spectral resolution of the FFT allowing us to ...

Page 5: ...the input frequency This spreading is called leakage Figure 5 A discontinuity in the folded finite time waveform leads to misleading results in the FFT There are many windowing techniques in use today to minimize this problem Figure 6 shows an FFT plot of the same data used in Figure 5 but using the Hanning windowing function Note the improved dynamic performance over no windowing as in Figure 5 T...

Page 6: ...6 http www national com 5 0 Hardware Documentation Please see the attached pages for a board layout hardware schematic and Bill of Materials ...

Page 7: ...7 http www national com ...

Page 8: ...7 1 C27 0 1uF 8 2 JP1 JP2 HEADER 3 9 1 JP3 HEADER 2 10 1 JP4 Logic Analyzer 11 1 JS1 CONN TRBLK 4 12 1 J1 Vert PCB mount 13 1 J2 FUTUREBUS_96 14 4 L1 L2 L3 L4 EXC CET103U 15 4 R1 R5 24 9 16 1 R4 49 9 17 1 R6 100K 18 11 R7 R8 R9 R10 R11 R12 R13 49 9 R14 R15 R16 R17 19 1 TP1 CLOCK 20 1 TP2 VIN 21 1 TP3 VCOM 22 1 TP4 VIN 23 1 TP5 VIN 24 1 TP6 VDDA 25 2 TP7 TP8 GND 26 1 TP9 VDDIO 27 1 TP10 VCC_Bfr 28 ...

Page 9: ...SIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical...

Page 10: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

Page 11: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADC10080EVAL ...

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