Figure 2b. ADC 08100 Evaluation Board Clock source
R40
330
4
6
1
3
2
J4
CLK SEL
C27
1uF
14
8
1
7
osc
D
GND
Vcc
OUT
Y1
100MHz
-5V
1
2
3
-5V
R29
47
R30
240
R33
330
R32
47
R37
330
R35
47
C25
1uF
R23
47
R22
330
R21
330
Q4
NTE65
Q5
NTE65
+5VA
C26
1uF
R25
47
R27
130
+5V
R41
Not
used
C32
short
R41A
4.7k
Q5
2N3904
ADC_CLK
λ
+5V
D4
RED LED
3
4
9
12
8
D
CC
__
CE
VCC
S
Q
_
Q
R
VEE
7 2
5 10
U8A
MC10H131FN
19
18
13
12
14
D
CC
__
CE
VCC
S
Q
_
Q
R
VEE
15 20
17 10
U8B
MC10H131FN
R31
510
-5V
R38
510
-5V
-5V
-5V
R34
47
R36
47
R39
510
-5V
-5V
+5V
C28
1uF
C30
1uF
C31
1uF
OUT
__
IN
IN
18
19
17
10
12
OUT
__
IN
IN
13
14
15
OUT
__
IN
IN
8
9
7
U7A
MC10H125FN
U7B
MC10H125FN
U7C
MC10H125FN
U7D
MC10H125FN
R28
47
R24
47
R26
510
-5V
C24
1uF
100MHz-2
50MHz
100MHz
_______
100MHz
[ NOT USED ]
[ NOT USED ]
HP1
HP2
OUT
__
IN
IN
3
4
5
2
20
R26A
510
-5V
C29
1uF
C23
1uF
C33
Not
used
1
1
h
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