National Instruments VXI-MXI User Manual Download

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VXI-MXI

User Manual

October 1993 Edition

Part Number 320222-01

Summary of Contents for VXI-MXI

Page 2: ...8 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 65 33 70 Germ...

Page 3: ...egligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes...

Page 4: ...ference from the equipment to radio reception in commercial areas Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to c...

Page 5: ...Configuring the VXI MXI 3 1 The Metal Enclosure 3 4 VXIbus Slot 0 3 4 VXIbus Logical Address 3 6 VMEbus Request Level 3 7 VMEbus Timeout Value 3 8 VMEbus Timeout Chain Position 3 10 Interlocked Arbit...

Page 6: ...igger Mode Selection Register 4 41 Interrupt Status Control Register 4 45 Status ID Register 4 48 MXIbus Trigger Configuration Register 4 49 Trigger Synchronous Acknowledge Register 4 50 Trigger Async...

Page 7: ...s Address Data and Address Modifier Transceivers 6 11 MXIbus System Controller Functions 6 12 MXIbus Control Signals Transceivers 6 12 MXIbus Requester and Arbiter Circuitry 6 12 Appendix A Specificat...

Page 8: ...igger Input Termination Option Settings 3 22 Figure 3 19 Reset Signal Selection Settings 3 23 Figure 3 20 MXIbus System 3 24 Figure 3 21 MXIbus Terminating Networks 3 25 Figure 3 22 INTX Terminator Ex...

Page 9: ...Requirements 2 2 Table 2 3 VXI MXI VMEbus Compliance Levels 2 3 Table 3 1 MXIbus System Power Cycling Requirements 3 30 Table 4 1 VXI MXI Register Map 4 2 Table 5 1 Base and Size Combinations 5 3 Tab...

Page 10: ...and configuring a system using VXI MXIs Chapter 6 Theory of Operation contains a functional overview of the VXI MXI board and explains the operation of each functional block making up the VXI MXI App...

Page 11: ...ers 4 through 6 Related Documentation The following manuals contain information that you may find helpful as you read this manual IEEE Standard for a Versatile Backplane Bus VMEbus ANSI IEEE Standard...

Page 12: ...in a metal enclosure to improve EMI performance and to provide easy handling Because the enclosure includes cut outs to facilitate changes to switch and jumper settings it should not be necessary to...

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Page 15: ...s cycles to detect bus cycles that map across the MXIbus Similarly external MXIbus cycles are monitored to detect MXIbus cycles that map into the VXIbus system MXIbus devices can operate in parallel a...

Page 16: ...ster TTL and ECL Trigger line support All integrated circuit drivers and receivers used on the VXI MXI meet the requirements of both the VMEbus specification and the MXIbus specification Front Panel F...

Page 17: ...onal Equipment Equipment Part Number Type M1 MXIbus Cables Straight point connector to straight point connector 1 m 180758 01 2 m 180758 02 4 m 180758 04 8 m 180758 08 20 m 180758 20 Type M2 MXIbus Ca...

Page 18: ...ent file a claim with the carrier Retain the packing material for possible inspection and or for reshipment 2 Verify that the pieces contained in the package you received match the kit parts list Do n...

Page 19: ...ignals used by the VXI MXI and the electrical loading presented by the circuitry on the interface board in terms of device types and their part numbers Note Throughout this manual an asterisk followin...

Page 20: ...equirements of the MXIbus specification Table 2 2 lists the components used Table 2 2 MXIbus Transceiver Requirements Transceivers Component Designation Data Transceivers DS3862 Control Transceivers D...

Page 21: ...6 bit data path to configuration registers or MXIbus D32 32 bit data path to MXIbus A16 Responds to 16 bit short I O addresses when specified on the address modifier lines A24 Responds to 24 bit memor...

Page 22: ...specified by the MXIbus address modifier lines BLT Generates block mode transfers when specified by the MXIbus address modifier lines RMW Can generate Read Modify Write cycles Interrupter Compliance L...

Page 23: ...rs These transceivers control the direction of the VMEbus data lines and meet VMEbus specifications for timing and signal loading VMEbus Control Signals Transceivers These transceivers control the dir...

Page 24: ...Configuration Registers Parity Check and Generation PAR AD31 0 VMEbus Data Transceivers D31 0 VXIbus System Controller Functions MXIbus System Controller Functions VMEbus Control Signals Transceivers...

Page 25: ...ne This state machine converts MXIbus cycles mapped through a MXIbus window into the VXIbus mainframe into VXIbus cycles MXIbus Address Data and Address These transceivers and associated circuitry con...

Page 26: ...2 VXI MXI INTX Daughter Card Option Block Diagram INTX Registers The INTX card has three onboard registers that reside in the VXI MXI configuration space the INTX Interrupt Configuration Register the...

Page 27: ...rrupt request level Similarly when a VMEbus interrupt line is driven out of the VXIbus mainframe across the INTX connection an interrupt handler in another VXIbus mainframe can generate an interrupt a...

Page 28: ...odule contains jumpers switches and slide switches that you can use to configure the following options VXIbus Slot 0 VXIbus Logical Address VMEbus Request Level VMEbus Timeout Value VMEbus Timeout Cha...

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Page 31: ...0 you must decide which device will be the Slot 0 device and reconfigure the other device for Non Slot 0 use Warning Do not install a device configured for Slot 0 into another slot without first reco...

Page 32: ...er to control and monitor the VXIbus MODID lines Slot 0 cards must also have 16 9 k pull up resistors on each VXIbus MODID line If the card is not in Slot 0 the MODID0 line on that card must be pulled...

Page 33: ...e VXIbus RM capability so do not set the logical address for the VXI MXI to 0 If you are configuring a multiple mainframe VXIbus MXIbus system refer to Chapter 5 Programming Considerations for instruc...

Page 34: ...request levels to request use of the VMEbus Data Transfer Bus DTB The VXI MXI requests use of the DTB whenever an external MXIbus device attempts a transfer that maps into the VXIbus mainframe The VXI...

Page 35: ...VXI MXI If there are multiple VXI MXI interfaces in a mainframe the BTO must be enabled on one of them and they must be in adjacent slots In the case of multiple VXI MXIs it is recommended that the BT...

Page 36: ...t of the mainframe initiating a MXIbus cycle The configuration of the VME BTO Chain Position jumper block selects how the VXIbus local bus is used to disable the VMEbus timeout when outward MXIbus tra...

Page 37: ...gure 3 8 W7 a One VXI MXI in Slot 0 Default Setting VME BTO Chain Position W7 b One VXI MXI Non Slot 0 VME BTO Chain Position Figure 3 8 VMEbus Timeout One VXI MXI in Mainframe When you have multiple...

Page 38: ...ings W7 a Slot 0 VXI MXI with BTO Multiple VXI MXIs in Mainframe Suggested Configuration VME BTO Chain Position W7 b Non Slot 0 VXI MXI with BTO the VXI MXI Closest to Slot 0 Multiple VXI MXIs in Main...

Page 39: ...TO Multiple VXI MXIs in Mainframe VME BTO Chain Position W7 b Non Slot 0 VXI MXI without BTO the VXI MXI Closest to Slot 0 Multiple VXI MXIs in Mainframe VME BTO Chain Position W7 c Non Slot 0 VXI MXI...

Page 40: ...aisy chained bus grant line Requesters closest to the Slot 0 device have higher priority therefore than devices installed in slots farther from Slot 0 In addition four bus request levels further prior...

Page 41: ...MXIbus System Controller slide switch selects whether or not the VXI MXI interface module is the MXIbus System Controller The MXIbus System Controller is the first device in the MXIbus daisy chain The...

Page 42: ...uments Corporation 3 15 VXI MXI User Manual MXIbus System Controller Enabled Disabled S4 a Not MXIbus System Controller Default Setting MXIbus System Controller Enabled Disabled S4 b MXIbus System Con...

Page 43: ...devices or in situations where one or more MXIbus devices use a large amount of MXIbus bandwidth Figure 3 13 shows how to position the jumper array to set the MXIbus System Controller timeout value Wh...

Page 44: ...s feature disabled Keep this option disabled if a device in your mainframe needs a large portion of the MXIbus bandwidth without interruptions from lower priority requesters In an unfair system the or...

Page 45: ...s shown in Figure 3 15 The VXI MXI is configured at the factory to be a Slot 0 device driving the CLK10 signal from the onboard oscillator If you are installing the VXI MXI in a slot other than Slot 0...

Page 46: ...MXI Installed in Slot 0 W10 W9 CLK10 Source Select c Do Not Source CLK10 VXI MXI Not Installed in Slot 0 W9 W10 CLK10 Source Select d Source CLK10 from INTX VXI MXI Installed in Slot 0 W9 Drive CLK10...

Page 47: ...MB is used as an input to receive a CLK10 signal to drive on the VXIbus or as an output to source the CLK10 signal to another VXIbus mainframe Figure 3 16 shows the two settings of slide switch S6 S6...

Page 48: ...Mapping Disabled Default Setting W2 W3 INTX CLK10 Routing W1 Receive CLK10 from INTX Drive CLK10 out INTX b CLK10 Mapped out of a Mainframe W2 W3 INTX CLK10 Routing W1 Receive CLK10 from INTX Drive CL...

Page 49: ...CLK10 Routing switches are enabled to map the VXIbus CLK10 signal to the INTX connector Warning Configuring more than one VXIbus device to drive the CLK10 lines or configuring both the VXI MXI and the...

Page 50: ...vice with VMEbus master capability must be installed in the VXIbus mainframe For the VXI MXI to perform as a MXIbus slave in A16 A24 or A32 space a slave VMEbus device with resources in those address...

Page 51: ...configuration Figure 3 20 shows an example of a daisy chained MXIbus system including terminators MXIbus System Controller PC AT VXI Mainframe VXI Mainframe VXI Mainframe MXIbus Cable 62 pin MXIbus Co...

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Page 53: ...em Controller PC AT VXI Mainframe VXI Mainframe VXI Mainframe MXIbus Cable 62 pin MXIbus Connectors Downstream MXIbus T erminator VXI MXI VXI MXI VXI MXI VXI MXI Upstream MXIbus T erminator VXI Mainfr...

Page 54: ...of the card with the card guides inside the mainframe Slowly push the VXI MXI straight into the slot until it seats in the backplane receptacles The front panel of the VXI MXI should be even with the...

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Page 57: ...ower is applied to each MXIbus device separately In this type of system you must power on devices starting with the device at the end of the MXIbus link opposite the MXIbus System Controller and progr...

Page 58: ...ds are configured The VXIbus specification has reserved the upper 16 KB of A16 space for configuration registers on VXIbus devices During system initialization the system Resource Manager scans the up...

Page 59: ...ansfer sizes for read write operations 8 bit 16 bit or 32 bit Table 4 1 shows the size of the registers on the VXI MXI All 16 bit registers can be accessed using 8 bit read write operations Register D...

Page 60: ...s IRQ Configuration Register 24 Read Write 16 bit Drive Triggers Read LA Register 26 Read Write 16 bit Trigger Mode Selection Register 28 Read Write 16 bit Interrupt Status Control Register 2A Read Wr...

Page 61: ...tus ID Interrupt Status Control Trigger Mode Register Drive Triggers Read LA MXIbus IRQ Configuration MXIbus Lock Register MXIbus Status Control Subclass Register VXI MXI Reserved INTX Utility Configu...

Page 62: ...n hardware as shown above Hard and soft resets have no effect on this register Bit Mnemonic Description 15 14r DEVCLASS Device Class Bits These bits indicate the device class of the VXIbus device as f...

Page 63: ...orporation 4 5 VXI MXI User Manual 11 0r MANID Manufacturer ID Bits This number uniquely identifies the manufacturer of the VXIbus device These bits are configured in hardware as hex FF6 the VXIbus ma...

Page 64: ...this device with a manufacturer s unique model code The bits in this register are set in hardware to the values shown above Hard and soft resets have no effect on this register Bit Mnemonic Descripti...

Page 65: ...ting to these bits 14r MODID MODID Line Status Bit This bit is zero when the device is selected by the MODID line and one when the device is not selected by the MODID line This bit is read only 13 10r...

Page 66: ...Hex B Revision F Hex A Revision G 3r RDY Ready Bit This bit is set to one in hardware to indicate that the device is ready to execute its full functionality This bit is read only 2r PASS Passed Bit Th...

Page 67: ...ption 15 14r w 0 Reserved Bits These bits are reserved and read back as zeros Write a zero when writing to these bits 13r w OUTEN MODID Output Enable Bits When this bit is set the VXI MXI is enabled t...

Page 68: ...cleared R W 7 6 5 4 3 2 1 LABASE7 LABASE6 LABASE5 LABASE4 LABASE3 LABASE2 LABASE1 LABASE0 0 R 15 14 13 12 11 10 9 0 LAEN LADIR 1 1 LASIZE2 LASIZE1 LASIZE0 8 0 LAEN LADIR 0 0 LASIZE2 LASIZE1 LASIZE0 W...

Page 69: ...from 0 to 7 the minimum size of a logical address window is 2 and the maximum size is 256 7 0r w LABASE 7 0 Logical Address Window Base Address Bits These bits in conjunction with the LASIZE bits defi...

Page 70: ...sses that map into the VXIbus where that range is LAHIGH range LALOW The VXIbus logical addresses mapped out of the VXI MXI are the inverse of this range that is MXIbus logical addresses greater than...

Page 71: ...nts Corporation 4 13 VXI MXI User Manual To accommodate 8 bit devices that write to this register the window is not enabled until the lower byte of the register is written Therefore 8 bit devices shou...

Page 72: ...is used to determine the range of addresses in the window The A16 Window Map Register has the following format when the CMODE bit is cleared R 15 14 13 12 11 10 9 0 A16EN A16DIR 1 1 A16SIZE2 A16SIZE1...

Page 73: ...window is 512 B and the maximum size is 48 KB A16SIZE 0 7 0r w A16BASE 7 0 A16 Window Base Address Bits These bits in conjunction with the A16SIZE bits define the base address of the A16 window for th...

Page 74: ...that map into the VXIbus where that range is A16HIGH range A16LOW The VXIbus A16 addresses mapped out of the VXI MXI are the inverse of this range that is MXIbus A16 addresses greater than or equal to...

Page 75: ...nts Corporation 4 17 VXI MXI User Manual To accommodate 8 bit devices that write to this register the window is not enabled until the lower byte of the register is written Therefore 8 bit devices shou...

Page 76: ...ollowing format when the CMODE bit is cleared R 15 14 13 12 11 10 9 0 A24EN A24DIR 1 1 A24SIZE2 A24SIZE1 A24SIZE0 8 0 A24EN A24DIR 0 0 A24SIZE2 A24SIZE1 A24SIZE0 W 7 6 5 4 3 2 1 A24BASE7 A24BASE6 A24B...

Page 77: ...aximum size is 16 MB 7 0r w A24BASE 7 0 A24 Window Base Address Bits These bits in conjunction with the A24SIZE bits define the base address of the A24 window for the VXI MXI The A24SIZE bits indicate...

Page 78: ...map into the VXIbus where that range is A24HIGH range A24LOW The VXIbus A24 addresses mapped out of the VXI MXI are the inverse of this range that is MXIbus A24 addresses greater than or equal to the...

Page 79: ...nts Corporation 4 21 VXI MXI User Manual To accommodate 8 bit devices that write to this register the window is not enabled until the lower byte of the register is written Therefore 8 bit devices shou...

Page 80: ...ollowing format when the CMODE bit is cleared R 15 14 13 12 11 10 9 0 A32EN A32DIR 1 1 A32SIZE2 A32SIZE1 A32SIZE0 8 0 A32EN A32DIR 0 0 A32SIZE2 A32SIZE1 A32SIZE0 W 7 6 5 4 3 2 1 A32BASE7 A32BASE6 A32B...

Page 81: ...BASE 7 0 A32 Window Base Address Bits These bits in conjunction with the A32SIZE bits define the base address of the A32 window for the VXI MXI The A32SIZE bits indicate the number of A32BASE bits tha...

Page 82: ...map into the VXIbus where that range is A32HIGH range A32LOW The VXIbus A32 addresses mapped out of the VXI MXI are the inverse of this range that is MXIbus A32 addresses greater than or equal to the...

Page 83: ...nts Corporation 4 25 VXI MXI User Manual To accommodate 8 bit devices that write to this register the window is not enabled until the lower byte of the register is written Therefore 8 bit devices shou...

Page 84: ...ping bits Writes to these bits have no effect 14 8r w EINT 7 1 EN Extended Interrupt Enable Bits Setting these bits individually enables the corresponding VMEbus IRQ lines to drive or receive the corr...

Page 85: ...Trigger Enable Bits Setting these bits individually enables the corresponding VXIbus TTL trigger lines to be mapped to the corresponding INTX trigger lines as specified by the corresponding ETRGxDIR...

Page 86: ...re reserved and read back as ones Write zeros to these bits when writing to this register 15r 0 Extended TTL Trigger Line Support This bit is set in hardware to zero to indicate that the INTX daughter...

Page 87: ...SFAIL line Clearing this bit disables the mapping of the INTX SYSFAIL line onto the VMEbus SYSFAIL line This bit is cleared on power up 2r w SYSFAILOUT Extended SYSFAIL Outward Bit Setting this bit en...

Page 88: ...ASS 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 These bits define the subclass of a VXIbus extended device The VXI MXI is a VXIbus Mainframe Extender Such devices are assigned the subclass code hex FFFC Hard and...

Page 89: ...ll treat a MXIbus cycle when the MXIbus Address Strobe is held low for multiple data transfers This bit is cleared on hard and soft resets If the MXIbus address modifiers label the transfer for block...

Page 90: ...zero when writing to these bits 13w ECL1EN ECL Trigger 1 Enable Bit Setting this bit enables the ECL Trigger line 1 to be mapped to the Trigger Out SMB connector or from the Trigger In SMB connector o...

Page 91: ...bus mode This mode of operation prevents deadlocks by allowing only one master of the entire system VXIbus and MXIbus at any given time When this bit is cleared the VXI MXI is configured to operate in...

Page 92: ...tatus Bit When this bit is set the VXIbus Trigger Interrupt signal TRIGINT in the Interrupt Status Register is active and is being driven across the MXIbus IRQ line When this bit is cleared the TRIGIN...

Page 93: ...roller This bit is cleared on a hard reset 2r MXBERR MXIbus Bus Error Bit If this bit is set the VXI MXI terminated the previous MXIbus transfer by driving the MXIbus BERR line This bit is cleared on...

Page 94: ...bits are reserved and read back as ones Write a zero when writing to these bits 0r w LOCKED Lock MXIbus or VXIbus Bit When this bit is set by a VXIbus device the MXIbus is locked by that device as so...

Page 95: ...ting these bits individually enables the corresponding VMEbus IRQ lines to drive or receive the MXIbus IRQ interrupt line The corresponding MIRQDIR bits select whether the MXIbus IRQ interrupt line is...

Page 96: ...Register Descriptions Chapter 4 VXI MXI User Manual 4 38 National Instruments Corporation MIRQxEN MIRQxDIR Routing 0 X Disabled 1 0 VME IRQ X drives MXI IRQ 1 MXI IRQ drives VME IRQ X...

Page 97: ...ine s after synchronizing the signal with the 10 MHz clock Reading these bits returns the current status of the corresponding trigger lines 7 0r LADD 7 0 Logical Address Status Bits Reading these bits...

Page 98: ...w DRVECL1 Drive ECL Trigger Line 1 Bit Setting this bit asserts the VXIbus ECL Trigger Line 1 after synchronizing the signal with the 10 MHz clock 0w DRVECL0 Drive ECL Trigger Line 0 Setting this bit...

Page 99: ...rigger lines for interrupt generation and trigger protocol generation These bits are cleared on soft and hard resets Bit Mnemonic Description 15 8r 1 Reserved Bits 5 4r 2w These bits are reserved and...

Page 100: ...Semi Sync Acceptor Mode the ITS 3 0 bits select the trigger line that the acceptor protocol is responding to The acceptor signal is driven onto the trigger line selected by the OTS 3 0 bits Write to...

Page 101: ...rigger signal specified by the OMS 2 0 bits OTS3 OTS2 OTS1 OTS0 Trigger Line 0 0 0 0 TTL Trigger Line 0 0 0 0 1 TTL Trigger Line 1 0 0 1 0 TTL Trigger Line 2 0 0 1 1 TTL Trigger Line 3 0 1 0 0 TTL Tri...

Page 102: ...n terms of the asynchronous protocol this bit is cleared after the acceptor has sent an acknowledge by asserting the selected trigger line 1w ASIE Asynchronous Interrupt Enable Bit When this bit is se...

Page 103: ...ly and reflect the status of the VMEbus IRQ lines The upper byte bits 15 through 8 of this register is cleared on a hard reset The lower byte bits 7 through 0 is cleared on hard and soft resets Bit Mn...

Page 104: ...ol Register 11w BKOFFIE Backoff Interrupt Enable Bit If this bit is set an interrupt is generated on the VMEbus interrupt line selected by the LINT 3 1 bits when a VMEbus Backoff condition occurs 10r...

Page 105: ...Status Bit If this bit is set an interrupt is currently driven on the VMEbus interrupt line selected by the LINT 3 1 bits because the VXIbus SYSFAIL line became set This bit is cleared on an interrup...

Page 106: ...value returned to the Interrupt Handler acknowledging an interrupt request driven by one of the DIRQ bits in the Interrupt Control Register Bit Mnemonic Description 15 0r w S 15 0 Status ID Value This...

Page 107: ...e the corresponding VXIbus TTL trigger lines to be mapped to the Trigger Out SMB connector or from the Trigger In SMB connector on the front panel as specified by the corresponding TRIGxDIR bit Cleari...

Page 108: ...X X X 8 W 7 6 5 4 3 2 1 X X X X X X X X 0 Writing any value to this register reinitializes the SSINT bit in the Trigger Mode Selection Register Trigger Asynchronous Acknowledge Register VXIbus Addres...

Page 109: ...6 5 4 3 2 1 I7 I6 I5 I4 I3 I2 I1 I0 0 These registers generate a VMEbus interrupt acknowledge cycle when they are read from a MXIbus device Bit Mnemonic Description 15 0r I 15 0 Interrupt Acknowledge...

Page 110: ...an be a VXIbus mainframe or a stand alone device for example a PC with a MXIbus interface that can operate as the system RM All MXIbus devices have address windows that connect them to the MXIbus syst...

Page 111: ...MXI VXIbus Mainframe VXI MXI VXIbus Mainframe VXI MXI MXIbus Interface Root Figure 5 1 VXIbus MXIbus System with Multiframe RM on a PC Level 1 Level 2 MXIbus Device MXIbus Device VXIbus Mainframe VXI...

Page 112: ...ping window on a MXIbus interface has Base and Size parameters associated with it when the CMODE bit in the MXIbus Control Register is cleared The Base bits define the base address for the window and...

Page 113: ...Size 7 Base6 Base5 Base4 Base3 Base2 Base1 Base0 Figure 5 3 Base and Size Combinations FF F0 EF E0 DF D0 CF C0 BF B0 AF A0 9F 90 8F 80 7F 70 6F 60 5F 50 3F 30 4F 40 2F 20 1F 10 0F 00 Size 1 Size 2 Si...

Page 114: ...ogical address map The example worksheets show numbers for using Base Size window formats For High Low format systems you do not need to round the range of addresses for each mainframe up to the next...

Page 115: ...et in Figure 5 10 for MXIbus 3 and entered the results into the worksheet for MXIbus 1 Figure 5 8 under the device VXIbus Mainframe 3 MXIbus 3 needs 32 logical addresses and the devices in VXIbus Main...

Page 116: ...the lowest available range of size 8 10 to 17 hex 9 Determine the range of addresses that will be occupied by each device in the first level MXIbus links Remember that the range of addresses occupied...

Page 117: ...MXI VXIbus Mainframe 4 VXI MXI VXIbus Mainframe 5 VXI MXI Level 1 Level 2 Multiframe Resource Manager MXIbus 1 MXIbus 2 MXIbus 3 Figure 5 5 Example VXIbus MXIbus System Table 5 2 Example VXIbus MXIbu...

Page 118: ...C0 BF B0 AF A0 9F 90 8F 80 7F 70 6F 60 5F 50 3F 30 4F 40 2F 20 1F 10 0F 00 VXIbus Mainframe 1 VXIbus Mainframe 6 VXIbus Mainframe 3 VXIbus Mainframe 4 VXIbus Mainframe 5 VXIbus Mainframe 2 Device A D...

Page 119: ...e 8 7 1 First Level MXIbus Link MXIbus 2 Fill in after completing charts on the following pages Total number of logical addresses required by MXIbus Link 8 Range 10 17 Round total number up to next po...

Page 120: ...power of two 32 25 Size 8 5 3 List other MXIbus links to this mainframe Number of logical addresses required by additional MXIbus links 0 Total number of logical addresses required by this device 23 R...

Page 121: ...ound total number up to next power of two 8 23 Size 8 3 5 Figure 5 9 Worksheet 3 for Example VXIbus MXIbus System MXIbus Link MXIbus 3 Device VXIbus Mainframe 4 Number of logical addresses required by...

Page 122: ...MXIbus Logical Address Map Use the worksheets on the following pages for analyzing your own VXIbus MXIbus system Follow the procedures used to fill out the worksheets for the sample VXIbus MXIbus syst...

Page 123: ...g pages Total number of logical addresses required by MXIbus Link Range Round total number up to next power of two Size First Level MXIbus Link Fill in after completing charts on the following pages T...

Page 124: ...l addresses required by this device Range Round total number up to the next power of two Size Device Number of logical addresses required by device Range Round total number up to the next power of two...

Page 125: ...l addresses required by this device Range Round total number up to the next power of two Size Device Number of logical addresses required by device Range Round total number up to the next power of two...

Page 126: ...l addresses required by this device Range Round total number up to the next power of two Size Device Number of logical addresses required by device Range Round total number up to the next power of two...

Page 127: ...tted lines can be used to add additional MXIbus links to Level 1 of the system or to connect a Level 2 MXIbus link to one of the devices on Level 1 Figure 5 11 presents one of these worksheets filled...

Page 128: ...Range IN Range OUT Device Device LA s Lower LA s Total LA s Range IN Range OUT Device Device LA s Lower LA s Total LA s Range IN Range OUT Device Device LA s Lower LA s Total LA s Range IN Range OUT...

Page 129: ...the system RM You should configure the A16 resources for your VMEbus boards in the lower 48 KB 0000 through BFFF hex of A16 space so that you do not interfere with VXIbus configuration space The logic...

Page 130: ...system the following pages include worksheets an address map diagram and an example The following steps are used in the example 1 Identify the RM Mainframe and the MXIbus levels of your system Determ...

Page 131: ...6 KB of A16 space so we assign it the bottom 16 KB of A16 space addresses 0 through 3FFF hex See Figure 5 14 for a pictorial representation of this assignment 10 Each first level MXIbus link is connec...

Page 132: ...to VXIbus Mainframe 4 and the next portion 5800 to 5BFF to VXIbus Mainframe 5 Therefore for VXIbus Mainframe 4 we assign Base 5000 Size 5 because 2 KB 256 28 5 and Direction In For VXIbus Mainframe 5...

Page 133: ...0 B VXIbus Mainframe 2 0 B VXIbus Mainframe 3 4 KB VXIbus Mainframe 4 2 KB VXIbus Mainframe 5 1 KB VXIbus Mainframe 6 2 KB BFFF B000 AFFF A000 9FFF 9000 8FFF 8000 7FFF 7000 6FFF 6000 5FFF 5000 4FFF 40...

Page 134: ...ress break A16 Window Base Size Direction First Level MXIbus Link Amount of A16 space required for devices connected to this VXI MXI Round up to next address break A16 Window Base Size Direction First...

Page 135: ...ow Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this device A16 space requirement for each second level MXIbus link connected to this device 1 2 Round up to next a...

Page 136: ...Direction Second Level VXI MXI 1 A16 Window Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this device A16 space requirement for each second level MXIbus link connec...

Page 137: ...the worksheets on the following pages for planning an A16 address map for your VXIbus MXIbus system Follow the procedures used to fill out the worksheets for the sample VXIbus MXIbus system BFFF B000...

Page 138: ...space required for devices connected to this VXI MXI Round up to next address break A16 Window Base Size Direction First Level MXIbus Link Amount of A16 space required for devices connected to this VX...

Page 139: ...indow Base Size Direction First Level VXI MXI A16 Window Base Size Direction Second Level VXI MXI 1 A16 Window Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this de...

Page 140: ...indow Base Size Direction First Level VXI MXI A16 Window Base Size Direction Second Level VXI MXI 1 A16 Window Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this de...

Page 141: ...indow Base Size Direction First Level VXI MXI A16 Window Base Size Direction Second Level VXI MXI 1 A16 Window Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this de...

Page 142: ...indow Base Size Direction First Level VXI MXI A16 Window Base Size Direction Second Level VXI MXI 1 A16 Window Base Size Direction Second Level VXI MXI 2 Device Amount of A16 space required by this de...

Page 143: ...t performs Step 2 If the multiframe RM is in a VXIbus mainframe it performs Step 2 for the mainframe in which the RM is installed 2 For the current mainframe the RM does the following A Scans all logi...

Page 144: ...ddress windows The system used is the example VXIbus MXIbus system shown in Figure 5 5 Table 5 5 shows the logical addresses we assigned to the devices in that system before bringing up the system MXI...

Page 145: ...DC devices in VXIbus Mainframe 4 to the lowest unused logical addresses No more VXI MXI interfaces are found The RM enables the logical address window for the VXI MXI in VXIbus Mainframe 4 with an inw...

Page 146: ...evices and defined ranges and finds the VXI MXI at logical address 10 Finds the Slot 0 device and uses it to move all DC devices in VXIbus Mainframe 6 to the lowest unused logical addresses No more VX...

Page 147: ...test administration hierarchy configuration and initiation of normal operation are handled as defined in the VXIbus specification A general purpose multiframe RM must wait five seconds before testing...

Page 148: ...ransfer bus arbiter It also sources the CLK10 signal and provides a MODID register as required for a VXIbus Slot 0 device The 16 MHz system clock driver is derived from an onboard clock with an accura...

Page 149: ...is set by a MXIbus device the VXI MXI interface will not release the VMEbus once it is granted the bus on the next transaction until the LOCK bit is cleared by a MXIbus device TTL and ECL Trigger Line...

Page 150: ...a Start signal When unasserted the trigger line indicates a Stop signal The VXI MXI can be configured either to drive its 10 MHz VXIbus CLK10 signal to other mainframes or to receive a 10 MHz CLK10 si...

Page 151: ...gister on the VXI MXI driving the MXIbus IRQ line to acknowledge the interrupt request 2 If the interrupt handler can generate MXIbus IACK cycles it is not necessary to poll MXIbus devices to find the...

Page 152: ...guration space on the remote VXI MXI The external device must know which VMEbus interrupt level it is servicing and read from the appropriate address Table 6 1 shows the designated addresses for VMEbu...

Page 153: ...are accessible from both the VXIbus and the MXIbus and are used to configure the VXI MXI These registers are described in detail in Chapter 4 Register Descriptions When the VXI MXI interface decodes a...

Page 154: ...second device The first device initiates the transfer with an address strobe and data strobe and the second device responds by asserting DTACK or BERR Figure 6 1 illustrates that a master device init...

Page 155: ...ed access L L H H H H A32 supervisory block transfer L L H H H L A32 supervisory program access L L H H L H A32 supervisory data access L L H L H H A32 nonprivileged block transfer L L H L H L A32 non...

Page 156: ...ata transfer portion of a MXIbus read cycle it asserts the VMEbus BERR signal to indicate to the VMEbus host that the data read contains an error Deadlock occurs when a VMEbus master is arbitrating fo...

Page 157: ...bus block transfers Block mode MXIbus operations improve MXIbus performance because a single address is sent at the beginning of a block mode cycle As block mode transfers can span over the address ra...

Page 158: ...o a maximum of 256 bytes in length The VXI MXI therefore will initiate a new block transfer after every 256 bytes of the MXIbus block transfer 2 If the RMWMODE bit is 0 and the address modifiers sent...

Page 159: ...vice in the MXIbus daisy chain it can still be configured as the MXIbus System Controller However any devices in the MXIbus daisy chain that are upstream from the MXIbus System Controller cannot be MX...

Page 160: ...ease the MXIbus the next time it is granted the bus on the next transaction until the LOCK bit is cleared by a VXIbus device A fairness feature ensures that all requesting devices will be granted use...

Page 161: ...nother mainframe In interlocked arbitration mode there can be only one master of the entire VXIbus MXIbus system at a time Devices in separate mainframes therefore cannot run operations in parallel Th...

Page 162: ...K Master Mode block transfers SBLOCK Slave Mode block transfers MRMW Master Mode Read Modify Write SRMW Slave Mode Read Modify Write PRI Prioritized arbitration ROR Release on Request bus requester IH...

Page 163: ...ransfers SBLOCK Slave Mode block transfers SC Optional MXIbus System Controller FAIR Optional MXIbus fair requester TERM Can accept MXIbus termination resistors IH Interrupt Handler IR Interrupt Reque...

Page 164: ...optional INTX daughter card Slot Requirements Single VXI C size slot VXI Keying Class Class 1 TTL Fully compatible with VXI specification Fully enclosed and shielded Reliability MTBF Contact Factory R...

Page 165: ...used in this manual to describe signals and terminology specific to MXIbus VMEbus VXIbus and register bits Refer also to the Glossary The mnemonic types in the key that follows are abbreviated to mean...

Page 166: ...A32 Window Size A 31 1 VBS VME Address Lines 31 through 1 ACCDIR B Access Direction ACFAIL B VXIbus ACFAIL Status ACFAIL VBS VME ACFAIL Signal ACFAILIE B VXIbus ACFAIL Interrupt Enable ACFAILIN B Exte...

Page 167: ...ESET DTACK VBS MBS Data Transfer Acknowledge DTRIG 7 0 B Drive VXIbus Trigger Lines E ECL0DIR B ECL Trigger Line 0 Direction ECL0EN B ECL Trigger 0 Enable ECL1DIR B ECL Trigger Line 1 Direction ECL1EN...

Page 168: ...0 B Logical Address Window Upper Bound LALOW 7 0 B Logical Address Window Lower Bound LASIZE 2 0 B Logical Address Window Size LINT 3 1 B Local Interrupt Line LNGMXSCTO B Long MXIbus System Controller...

Page 169: ...errupt Acknowledge S S 15 0 B Status ID SIZE MBS MXIbus Size Signal SSIE B Synchronous Interrupt Enable SSINT B Synchronous Interrupt Status Status ID VME VMEbus Interrupt Status Identification Data S...

Page 170: ...ator Power TRIGDIR 7 0 B Trigger Direction TRIGEN 7 0 B Trigger Enable TRIGIN B Trigger Input Status TRIGINT B Trigger Interrupt TRIGINTIE B Trigger Interrupt Enable TRIGOUT B Trigger Output Status TT...

Page 171: ...e easy handling Because the enclosure includes cut outs to facilitate changes to switch and jumper settings it should not be necessary to remove it under normal circumstances Should you find it necess...

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Page 175: ...59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Figure D 1 MXIbus Connector Table D 1 MXIbus Connector Signal Assignments Pin Signal Name Pin Signal Name Pin Signal Name 1 AM4 22 AD15 43 PAR 2 AM3...

Page 176: ...ite WR 1 40 Data Strobe DS 1 38 Data Acknowledge DTACK 1 41 Parity PAR 1 43 Arbitration MXIbus Busy BUSY 1 46 MXIbus Request BREQ 1 45 MXIbus Grant In GIN 1 60 MXIbus Grant Out GOUT 1 59 Interrupt Int...

Page 177: ...9 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 Figure D 2 INTX Connector Table D 3 INTX Connector Signal Assignments Pin Signal Name Pin Signal Name Pin Signal Name 1 Reserved 16 Reserved 31...

Page 178: ...INTX Trigger TRIG7 0 16 Diff Utility Lines INTX SYSRESET SYSRESET 1 O C INTX SYSFAIL SYSFAIL 1 O C INTX ACFAIL ACFAIL 1 O C System Clock INTX CLK10 CLK 2 Diff Power Ground GND 10 Termination Power TER...

Page 179: ...quick reference for systems such as the one in Figure E 1 which consists of two VXI mainframes connected by a single MXIbus link bus NATIONAL INSTRUMENTS Frame A Frame B Slot 0 Device bus NATIONAL INS...

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Page 184: ...7F hex The Resource Manager must be Logical Address 0 The VXI MXI is Logical Address 1 Ensure that no other devices in that frame have either of these logical addresses In addition no devices in Frame...

Page 185: ...day from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 800 433 3488 toll free U S and Canada Tec...

Page 186: ...g any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Use additional pages if necessary Name Company Address Fax Phon...

Page 187: ...__________ VMEbus Timeout Value _________________________________________________ VMEbus Timeout Chain Position _________________________________________________ Interlocked Bus Cycle Mode or Normal O...

Page 188: ...__________ VXI Interrupt Level s of Other Devices _________________________________________________ _________________________________________________ _________________________________________________...

Page 189: ...art Number 320222 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for you...

Page 190: ...located for use by VXI devices configuration registers This 16 KB region is referred to as VXI Configuration space A24 Space VXIbus address space equivalent to the VME 16 MB standard address space A32...

Page 191: ...ed not controlled by time signals Asynchronous A two device two line handshake trigger protocol using two consecutive Protocol even odd trigger lines a source acceptor line and an acknowledge line B B...

Page 192: ...s operated on as a single unit Most commonly consists of eight bits C C Celsius Clearing Replacing the information in a register storage location or storage unit with zeros or blanks CLK10 A 10 MHz 10...

Page 193: ...st slot and ending with the last slot Data Strobe A signal used to inform a slave that valid data exists on the bus or used to request that a slave place data on the bus Data Transfer Bus DTB one of f...

Page 194: ...tion These devices have a subclass register within their configuration space that defines the type of extended device The VXI MXI is an extended class mainframe extender device F Fair Requester A MXIb...

Page 195: ...vice Interrupt Handler A functional module that detects interrupt requests generated by interrupters and performs appropriate actions Interrupter A device capable of asserting interrupts and respondin...

Page 196: ...transfer rate Memory Device A VXIbus device that not only has configuration registers but also has memory that is accessible through addresses on the VME VXI data transfer bus Message Based An intelli...

Page 197: ...required for a VMEbus system It includes 24 address lines 16 data lines and all control arbitration and interrupt signals P2 A second VMEbus connector providing 32 bits of address and data In VXI the...

Page 198: ...multiple device handshake trigger protocol Protocol Servant A device controlled by a Commander there are Message Based and Register Based Servants Setting To place a binary cell into the 1 state non z...

Page 199: ...specify the reason for interrupting Supervisory Access One of the defined types of VMEbus data transfers indicated by certain address modifier codes Synchronous A communications system that follows t...

Page 200: ...ersatile Backplane Bus VXIbus VMEbus Extensions for Instrumentation VXIbus System A functional module with circuitry that generates the 16 MHz system Controller clock provides the VMEbus arbiter and t...

Page 201: ...bit 4 19 A24DIR bit 4 18 4 19 A24EN bit 4 18 4 19 A24HIGH 7 0 bit 4 20 A24LOW 7 0 bit 4 20 A24SIZE 2 0 bit 4 19 A32 Window Map Register 4 22 to 4 25 bit descriptions 4 22 to 4 23 4 24 configuring for...

Page 202: ...ty Line Support 0 4 28 FAIR 4 34 I 15 0 4 51 INTLCK 4 33 IRQ 7 1 4 47 ITS 3 0 4 42 LABASE 7 0 4 11 LADD 7 0 4 39 LADIR 4 10 4 11 LAEN 4 10 4 11 LAHIGH 7 0 4 12 LALOW 7 0 4 12 LASIZE 2 0 4 11 LINT 3 1...

Page 203: ...System Controller 3 14 to 3 15 MXIbus System Controller timeout 3 16 parts locator diagram VXI MXI C 2 VXI MXI with INTX 3 3 VXI MXI without INTX 3 2 removing metal enclosure 3 4 reset signal selecti...

Page 204: ...g the VXI MXI interface module 1 7 interlocked arbitration mode configuration 3 13 to 3 14 Interrupt and Timing Extension INTX daughter card See INTX daughter card interrupt circuitry definition 2 7 i...

Page 205: ...guration format 5 3 to 5 4 basic configurations illustration 5 2 examples 5 8 to 5 9 high low configuration format 5 5 multiframe RM operation 5 35 to 5 38 A24 and A32 addressing windows 5 38 example...

Page 206: ...sfer responses for VMEbus address modifiers 6 8 VMEbus MXIbus transfer size comparison 6 9 VMEbus to MXIbus address modifier line map 6 7 MXIbus requester and arbiter circuitry definition 2 7 theory o...

Page 207: ...tility Configuration Register 2 8 4 28 to 4 29 Logical Address Window Register 4 10 to 4 13 MODID Register 4 9 Subclass Register 4 30 request level VMEbus 3 7 to 3 8 requester and arbiter circuitry VM...

Page 208: ...6 3 TTL trigger lines 6 2 to 6 3 VMEbus address and address modifier transceivers 6 1 control signal transceivers 6 2 data transceivers 6 1 requester and arbiter circuitry 6 2 VXI MXI configuration re...

Page 209: ...ew 1 4 to 1 5 support signals for VMEbus 1 4 to 1 5 unpacking 1 7 VMEbus compliance levels 2 3 to 2 4 VMEbus modules 2 2 to 2 3 VXIbus capability codes A 1 VXIbus configuration registers definition 2...

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