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Chapter 4
Analog Input
©
National Instruments Corporation
4-17
Using a Delay from Sample Clock to Convert Clock
When
u
sing an internally generated AI Convert Clock, yo
u
also can specify
a config
u
rable delay from AI Sample Clock to the first AI Convert Clock
p
u
lse within the sample. By defa
u
lt, this delay is three ticks of AI Convert
Clock Timebase.
Fig
u
re 4-9 shows the relationship of AI Sample Clock to AI Convert Clock.
Figure 4-9.
AI Sample Clock and AI Convert Clock
Other Timing Requirements
The sample and conversion level timing of USB-621
x
devices work s
u
ch
that clock signals are gated off
u
nless the proper timing req
u
irements are
met. For example, the device ignores both AI Sample Clock and AI
Convert Clock
u
ntil it receives a valid AI Start Trigger signal. Once the
device recognizes an AI Sample Clock p
u
lse, it ignores s
u
bseq
u
ent AI
Sample Clock p
u
lses
u
ntil it receives the correct n
u
mber of AI Convert
Clock p
u
lses.
Similarly, the device ignores all AI Convert Clock p
u
lses
u
ntil it recognizes
an AI Sample Clock p
u
lse. Once the device receives the correct n
u
mber of
AI Convert Clock p
u
lses, it ignores s
u
bseq
u
ent AI Convert Clock p
u
lses
u
ntil it receives another AI Sample Clock. Fig
u
res 4-10, 4-11, 4-12,
and 4-13 show timing seq
u
ences for a fo
u
r-channel acq
u
isition (
u
sing AI
channels 0, 1, 2, and 3) and demonstrate proper and improper seq
u
encing
of AI Sample Clock and AI Convert Clock.
AI Convert Clock Time
bas
e
AI
Sa
mple Clock
AI Convert Clock
Del
a
y
From
Sa
mple
Clock
Convert
Period