Chapter 2
Configuration and Installation
2-46
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Figure 2-19 illustrates a read of the SCXI-1121 Module ID Register.
Figure 2-19.
SCXI-1121 Module ID Register Timing Diagram
For further details on programming these signals, refer to Chapter 5,
SLOT0SEL*
SS*
SERCLK
0
0
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
SERDATOUT
T
delay
byte 0 = 2
byte 3 = 0
byte 2 = 0
byte 1 = 0
T
delay
SS* high to SERDATOUT high
350 nsec maximum
