Chapter 2
Configuration and Installation
© National Instruments Corporation
2-27
SCXI-1100 User Manual
0
1
0 0
1
1
0
1
1
Chassis ID = 9
Slot 11
SERDATIN
SS*X
Chassis Y
SS*11
Chassis 9
SERCLK
SLOT0SEL*
T
ss_dis
T
ss_en
T
clk_wait
T
slot0sel*_wait
T
ss _ dis
SLOT0SEL* low to SS* disabled
200 nsec maximum
T
clk _ wait
SLOT0SEL* low to first rising edge on SERCLK
75 nsec minimum
T
slot0sel* _ wait
Last rising edge on SERCLK to SLOT0SEL* high
250 nsec minimum
T
ss _ en
SLOT0SEL* high to SS* enabled
350 nsec maximum
Figure 2-10. Slot-Select Timing Diagram
To write the 16-bit slot-select number to Slot 0, perform the following steps:
1. Initial conditions:
SERDATIN = don't care.
DAQD*/A = don't care.
SLOT0SEL* = 1.
SERCLK = 1.
2. Clear SLOT0SEL* to 0. This deasserts all SS* lines to all modules in all chassis.
3. For each bit, starting with the MSB, perform the following actions:
a. Set SERDATIN = bit to be sent. These bits are the data that is being written to the
Slot-Select Register.
b. Clear SERCLK to 0.
c. Set SERCLK to 1. This rising edge clocks the data.
4. Set SLOT0SEL* to 1. This asserts the SS* line of the module whose slot number was
written to Slot 0. If you are using multiple chassis, only the appropriate slot in the chassis
whose address corresponds to the written chassis number is selected. When no
communication is taking place between the data acquisition board and any modules, write
zero to the Slot-Select Register to ensure that no accidental writes occur.
Figure 2-11 shows the timing requirements on the SERCLK and SERDATIN signals. You must
observe these timing requirements for all communications. T
delay
is a specification of the
SCXI-1100.