background image

2-12

|

ni.com

Chapter 2

Using the PXIe-4309

Sample Timing Modes

The PXIe-4309 supports four timing modes that fall into two categories: software-timed and 
hardware-timed.

Note

Software-timed, hardware timed single point (HWTSP), and external sample 

clock use single sample acquisition to minimize latency. Refer to the 

Single Convert 

Acquisition

 section for more information.

Software-Timed Acquisitions

Software controls the rate of the acquisition. Software sends a separate command to the 
hardware to acquire each sample. In NI-DAQmx, software-timed acquisitions are referred to as 
having on-demand timing. Software-timed acquisitions are also referred to as immediate or 
static acquisitions and are typically used for reading a single sample of data.

Hardware-Timed Acquisitions

A digital hardware signal (AI Sample Clock) controls the rate of the acquisition. This signal can 
be generated internally by the PXIe-4309 or provided externally.

Hardware-timed acquisitions have several advantages over software-timed acquisitions:

The time between samples can be much shorter.

The timing between samples is deterministic.

Hardware-timed acquisitions can use hardware triggering.

Hardware-timed operations can be buffered or HWTSP. A buffer is a temporary storage in 
computer memory for to-be-transferred samples.

Buffered

—In a buffered acquisition, data is moved from the onboard FIFO memory of the 

DAQ device to a PC buffer using DMA before it is transferred to application memory. 
Buffered acquisitions typically allow for much faster transfer rates than HWTSP 
acquisitions because data is moved in large blocks, rather than one point at a time.
One property of buffered I/O operations is the sample mode. The sample mode can be either 
finite or continuous:

Finite sample mode acquisition refers to the acquisition of a specific, predetermined 
number of data samples. Once the specified number of samples has been read, the 
acquisition stops. If you use a reference trigger, you must use finite sample mode.

Continuous acquisition refers to the acquisition of an unspecified number of samples. 
Instead of acquiring a set number of data samples and stopping, a continuous 
acquisition continues until you stop the operation. Continuous acquisition is also 
referred to as double-buffered or circular-buffered acquisition.
If data cannot be transferred across the bus fast enough, the FIFO becomes full. For 
more information refer to 

NI-DAQmx Help

.

Summary of Contents for SC Express PXIe-4309

Page 1: ...SC Express PXIe 4309 User Manual 32 Ch 8 ADC 2 MS s 18 28 bit Flexible Resolution PXI Analog Input Module PXIe 4309 User Manual May 2017 377024A 01...

Page 2: ...mail addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 866 ASK MYNI 275 6964 For further support information refer t...

Page 3: ...ESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING TH...

Page 4: ...es independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology re...

Page 5: ...le Modes 2 9 Averaging Acquisition 2 9 Single Convert Acquisition 2 11 Sample Timing Modes 2 12 Software Timed Acquisitions 2 12 Hardware Timed Acquisitions 2 12 Offset Error Cancellation Techniques 2...

Page 6: ...gle Convert Acquisition of a Single Channel 2 11 Figure 2 10 Single Convert Acquisition of Two Channels on the Same ADC 2 11 Figure 2 11 Analog Input Auto Zero 2 13 Figure 2 12 Analog Input Chopping 2...

Page 7: ...gregate up to 4 channels per ADC Installation Refer to the PXIe 4309 and TB 4309 ST TB 4309 MT Getting Started Guide and Terminal Block Specifications document for step by step installation instructio...

Page 8: ...lation media Connecting Signals This section provides information regarding the connection of voltage signals Caution To ensure the specified EMC performance operate this product only with shielded tw...

Page 9: ...Input Channel Source Impedance Best measurement performance is achieved with source impedance of 50 or lower refer to the Source Impedance Error section of the PXIe 4309 Specifications for information...

Page 10: ...he AIn lead wire to a minimum Common Mode Noise Floating power supplies inject common mode current onto its floating ground To minimize the effect of this current on measurement noise keep the DC resi...

Page 11: ...of the front connector of the PXIe 4309 Refer to the I O Connector Signal Descriptions section for definitions of each signal Refer to the PXIe 4309 and TB 4309 ST TB 4309 MT Getting Started Guide an...

Page 12: ...D AI21 AI5 25 AI13 AI21 AI5 24 AI13 AI29 AI29 23 GND AI17 AI1 22 AI9 AI17 AI1 21 AI9 AI25 AI25 20 GND NC NC 19 REF NC NC 18 REF NC NC 17 GND AI18 AI2 16 AI10 AI18 AI2 15 AI10 AI26 AI26 14 GND AI22 AI6...

Page 13: ...VD Reserved for communication with the accessory PFI 0 1 Input Output Configurable 5 0 V tolerant digital input or 3 3 V digital output for sending or receiving trigger and synchronization signals PFI...

Page 14: ...total of 32 input channels Figure 2 6 shows the block diagram of the PXIe 4309 Figure 2 6 PXIe 4309 Block Diagram AI0 AI16 AI8 AI24 PFI GND PFI1 PFI0 Floating Circuitry 1 of 8 SAR ADC Low Pass Filter...

Page 15: ...iple Channels per ADC The PXIe 4309 can sample 32 input channels when multiple channel per ADC are selected In this mode of operation each ADC can scan through four independent input channels up to an...

Page 16: ...aging Acquisition and Single Convert Acquisition sections Convert is a single ADC quantized digitization of the input signal Sample is the data returned from hardware Averaging Acquisition The PXIe 43...

Page 17: ...settling time increases as the aggregate sample rate decreases to allow for more settling time to reduce settling and ghosting errors Figure 2 8 Multiple Channel Averaging Table 2 4 shows the max sam...

Page 18: ...g and ghosting errors Figure 2 10 Single Convert Acquisition of Two Channels on the Same ADC Table 2 5 shows the max sampling rate based on the maximum number of channels per ADC Table 2 5 Maximum Sam...

Page 19: ...ardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or HWTSP A buffer is a temporary storage in computer memory for to be transferred samples Buffered In a...

Page 20: ...the Info Code daqhwtsp Offset Error Cancellation Techniques The PXIe 4309 supports two types of offset error cancellation techniques auto zero and chopping Auto Zero Each signal conditioning path of...

Page 21: ...lay Note The start delay is in units of 100 MHz timebase ticks by default With auto zero set to once the offset error temperature coefficient is the same as with auto zero none making Auto Zero once a...

Page 22: ...ements the offset error of the signal conditioning path adds to the measured voltage as follows VAI0 VS1 VO VAI16 VS1 VO Using these measurements it is possible to cancel out the offset error of the s...

Page 23: ...rate when chopping is enabled based on the maximum number of chopping channels per ADC Table 2 7 AI Channel Connection Pairing for Chopping Channels Chopping Channel AI Channel ai0 ai0 ai16 ai1 ai1 ai...

Page 24: ...clock which can be locked to the PXIe backplane 100 MHz clock to synchronize multiple modules External Clock The PXIe 4309 sample clock can be driven from external sources by either PXI_TRIG 0 7 PFI...

Page 25: ...Reference Trigger ai ReferenceTrigger AI Pause Trigger ai PauseTrigger AI Sample Clock Timebase ai SampleClockTimebase Note The polarity of PFI inputs is configurable for most functions Note Pause tr...

Page 26: ...a low to high transition for a custom filter with N set to 5 Figure 2 14 Low to High Transition for a Custom Filter with N Set to 5 Table 2 9 shows the debouncing filters supported by the PXIe 4309 T...

Page 27: ...l count for your measurements In addition the PXIe 4309 can synchronize with 62XX M Series and 63XX X Series devices modules such as the PXI 6289 and PXIe 6363 respectively Refer to the Reference Cloc...

Page 28: ...sories or terminal blocks The RSVD pins on the I O connector provide power to the accessories as well as digital communication lines This allows software to detect when accessories are inserted or rem...

Page 29: ...0 cannot be used as a reference clock for SC Express modules PXI Triggers A PXI PXIe chassis provides eight bused trigger lines to each module in a system Triggers may be passed from one module to ano...

Page 30: ...I Express system timing controller and a peripheral device Using multiple connections simplifies the creation of applications because of the increased routing capabilities Table 3 1 describes the thre...

Page 31: ...fy your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni c...

Page 32: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

Reviews: