![background image](http://html.mh-extra.com/html/national-instruments/pxie-6674/pxie-6674_user-manual_709612015.webp)
on page 15 and
on page 16 summarize the routing features of the
PXIe-6674. The remainder of this chapter details the capabilities and constraints of the routing
architecture.
Figure 4. High-Level Schematic of PXIe-6674 Signal Routing Architecture
÷2
N
÷2
M
÷2
N
÷2
M
Selection
Circuitry
PXI_STAR 0
PXI_STAR 1
PXI_STAR 16
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
PXI_TRIG 0
PXI_TRIG 1
PXI_TRIG 7
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
3
SYNCHRONIZATION
CLOCKS for PFI<0..5>
and PFI_LVDS<0..2>
53
SOURCE
*
3
*
PXI_STAR<0..16>, PXI_TRIG<0..7>,
PFI<0..5>, PFI_LVDS<0..2>,
PXIe_DSTARC<0..16>, Steady
Logic, and Software Trigger are
routed to SOURCE of each Selection
Circuitry block.
SYNCHRONIZATION CLOCKS
for PXI_STAR<0..16>, PXI_TRIG<0..7>,
and PXIe-DSTARB<0..16>
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
PFI 0
PFI 1
PFI 2
PFI 3
PFI 4
PFI 5
PFI_LVDS 0
PFI_LVDS 1
PFI_LVDS 2
Selection
Circuitry
PXIe_DSTARB 0
PXIe_DSTARB 1
PXIe_DSTARB 16
Selection
Circuitry
Selection
Circuitry
CLKIN
OCXO
Clock Generation
PXIe-CLK100
PXI_CLK10
CLKIN
OCXO
Clock Generation
PXIe-CLK100
PXI_CLK10
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
on page 16 provides a more detailed view of the selection circuitry referenced in
on page 15.
PXIe-6674 User Manual
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© National Instruments
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