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NI PXI-6683 Series User Manual
Given the architecture of the PXI trigger bus, triggering signals do not reach each slot at
precisely the same time. A difference of several nanoseconds can occur between slots, especially
in larger PXI chassis (which can have buffers between segments). This delay is not a problem
for many applications. However, if your application requires tighter synchronization, use the
PXI_STAR triggers (see next section), or use the PXI trigger bus synchronous to PXI_CLK10.
The multi-drop nature of the PXI trigger bus can introduce signal integrity issues. Therefore,
National Instruments does not recommend the use of PXI_Trigger lines for clock distribution.
The preferred method for clock distribution is the use of the PXI_STAR triggers. However, the
NI PXI-6683 Series does support routing of clocks to the PXI_Trigger lines, in case you must
use them.
For each PXI_Trigger line configured as an output in the NI PXI-6683 Series, the signal source
can be independently selected from the following options:
•
PFI<0..2>
•
Another PXI trigger line (PXI_TRIG<0..7>)
•
PXI_STAR<0..12>
•
Future time events
•
PXI_CLK10
•
Ground
Tip
Invert Ground to get a logic high.
The PXI trigger outputs may be synchronized to CLK10 except when routing future time events.
Refer to the
section for more information about the
synchronization clock.
Using the PXI Star Triggers (NI PXI-6683 only)
There are up to 13 PXI star triggers per chassis. Each trigger line is a dedicated connection
between the system timing slot and one other slot. The
PXI Specification
, Revision 2.1, requires
that the propagation delay along each star trigger line be matched to within 1 ns. A typical upper
limit for the skew in most NI PXI chassis is 500 ps. The low skew of the PXI star trigger bus is
useful for applications that require triggers to arrive at several modules nearly simultaneously.
The NI PXI-6683 is able to route low skew triggers to the PXI_Star lines from any PFI line.
The star trigger lines are bidirectional, so signals can be sent to the system timing slot from a
module in another slot or from the system timing slot to the other module.