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National Instruments Corporation
17
8-Slot NI PXIe-1062Q Backplane Installation Guide
Input amplitude
Connector J27 .......................... 200 mV
pp
to 5 V
pp
, 10 MHz
squarewave or sinewave
Slot 2........................................ 5 V or 3.3 V, 10 MHz TTL signal
Input impedance.............................. 50
Ω
± 5
Ω
(rear connector)
Maximum jitter introduced
by backplane circuitry..................... 1 ps RMS in 10 Hz to 1 MHz
range
External clock output, connector J27
Connector........................................ Connector J27 on rear of
backplane (ground-referenced)
Output amplitude ............................ 1 V
pp
±20% squarewave into 50
Ω
2 V
pp
into open circuit
Output impedance ........................... 50
Ω
± 5
Ω
Pinouts
This section describes the connector pinouts for the NI PXIe-1062Q
chassis backplane.
Table 4 shows the XP1 connector pinout for the system controller slot.
Table 5 shows the XP2 connector pinout for the system controller slot.
Table 6 shows the XP3 connector pinout for the system controller slot.
Table 7 shows the XP4 connector pinout for the system controller slot.
Table 8 shows the TP2 connector pinout for the system timing slot.
Table 9 shows the XP3 connector pinout for the system timing slot.
Table 10 shows the XP4 connector pinout for the system timing slot.
Table 11 shows the P1 connector pinout for the peripheral slots.
Table 12 shows the P2 connector pinout for the peripheral slots.
Table 13 shows the P1 connector pinout for the hybrid peripheral slots.
Table 14 shows the XP3 connector pinout for the hybrid peripheral slots.
Table 15 shows the XP4 connector pinout for the hybrid peripheral slots.
