NI 6583R User Guide and Specifications
26
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Generation (Data, Clock, and PFI Channels)
Output impedance ..................................................50
Ω,
nominal
Maximum per channel DC drive strength
V
CC
1.2 V .......................................................±6 mA
V
CC
1.4 V to 1.6 V .........................................±12 mA
V
CC
1.65 V to 1.95 V .....................................±16 mA
V
CC
2.3 V to 3.3 V .........................................±18 mA
Output protection ...................................................Single-ended I/O can indefinitely sustain a short to
any voltage between
−
0.5 V and V
CC
+ 0.5 V with a
current not exceeding 30 mA.
Acquisition (Data, STROBE, and PFI Channels)
Input impedance.....................................................50 k
Ω,
nominal
Input protection
......................................................−
0.5 V to 4.6 V
Note
Internal diode clamps may begin conducting outside the 0 V to V
CC
range.
LVDS Channels (DDC B)
(Consistent with TI part number SN65LVDM180)
Number of programmable I/O voltage levels ........None
Power-up state........................................................Drivers disabled, 100
Ω
differential impedance with
300 k
Ω
to 3.3 V
Typical data rate .....................................................300 Mb/s
Table 7.
Generation Voltage Levels (100
µ
A load)
Generation
Voltage Levels
Low Voltage Levels
High Voltage Levels
Characteristic
Maximum
Minimum
Characteristic
V
CC
1.2 V to 3.3 V
0 V
200 mV
V
CC
– 200 mV
V
CC
Table 8.
Acquisition Voltage Threshold
Acquisition Voltage Levels
Low Voltage Threshold
High Voltage Threshold
Minimum
Maximum
V
CC
1.2 V to 1.95 V
0.35
×
V
CC
0.65
×
V
CC
V
CC
1.95 V to 2.7 V
0.7 V
1.6 V
V
CC
2.7 V to 3.3 V
0.8 V
2.0 V
Summary of Contents for NI 6583R
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