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Glossary

©

 National Instruments Corporation

G-3

653X User Manual

channel

Pin or wire lead to which you apply or from which you read the analog or 
digital signal. For digital signals, you group channels to form ports. Ports 
usually consist of either four or eight digital channels.

CompactPCI

core specification defined by the PCI Industrial Computer Manufacturer’s 
Group (PICMG)

compiler

A software utility that converts a source program in a high-level 
programming language, such as LabVIEW, Basic, C or Pascal, into an 
object or compiled program in machine language. Compiled programs run 
10 to 1,000 times faster than interpreted programs. Some languages, such 
as Java, are compiled to an intermediate language that is interpreted at run 
time.

control signals

Signals that regulate/control the timing of your data transfer in handshaking 
I/O and pattern I/O. There are four control signals in your 653

X

device: 

ACK (STARTTRIG), REQ, STOPTRIG, and PCLK.

counter/timer

 a circuit that counts external pulses or clock pulses (timing)

CPULL

A user-configurable 2.2 k

Ω

 internal resistor for control lines. You can 

connect the line to +5 VDC (

pull up

) or connect the line to ground (

pull 

down

).

current sinking

the ability to dissipate current for analog or digital signals

current sourcing

the ability to supply current for analog or digital signals

D

DAQ

Data Acquisition—Collecting and measuring electrical signals from 
sensors, transducers, and test probes or fixtures and inputting them to a 
computer for processing. Also refers to collecting and measuring the same 
kinds of electrical signals with analog-to-digital and/or digital devices 
plugged into a PC, and possibly generating control signals with 
digital-to-analog and/or digital devices in the same PC.

Data In Valid

data generated by peripheral device that is ready for input to the 653

X

 

device

DC

direct current

Summary of Contents for NI 653x

Page 1: ...DAQ 653X User Manual High Speed Digital I O Devices for PCI PXI CompactPCI AT EISA and PCMCIA Bus Systems 653X User Manual January 2001 Edition Part Number 321464C 01...

Page 2: ...725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 280 7...

Page 3: ...or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligen...

Page 4: ...ommunications DOC Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Co...

Page 5: ...Directives Readers in the EU EEC EEA must refer to the Manufacturer s Declaration of Conformity DoC for information pertaining to the CE Mark compliance scheme The Manufacturer includes a DoC for most...

Page 6: ...avoid injury data loss or a system crash This icon denotes a warning which advises you of precautions to take to avoid being electrically shocked bold Bold text denotes items that you must select or c...

Page 7: ...6533 for PCMCIA 1 8 Configuring the 653X 1 8 In Windows 1 8 In Mac OS 1 9 Chapter 2 Using Your 653X Choosing the Correct Mode for Your Application 2 1 Controlling and Monitoring Static Digital Lines...

Page 8: ...he Transfer Rate 2 18 Deciding How to Start and Stop Data Transfer Triggering 2 19 Start and Stop Trigger 2 20 Choosing Continuous or Finite Data Transfer 2 21 Finite Transfers 2 21 Continuous Input 2...

Page 9: ...chronous Protocols 3 12 Using the 8255 Emulation Protocol 3 12 Using the Level ACK Protocol 3 18 Using Protocols Based on Signal Edges 3 24 Using the Trailing Edge Protocol 3 25 Appendix A Specificati...

Page 10: ...transfer data to from this memory at a guaranteed rate This memory feature removes the dependency on the host computer bus for applications that require guaranteed transfer rates The PCI PXI 7030 653...

Page 11: ...ng devices AT DIO 32HS DAQCard 6533 for PCMCIA PCI 6534 PCI DIO 32HS PXI 6533 PXI 6534 PCI or PXI 7030 6533 RT Series DAQ device 653X User Manual NI DAQ for PC compatibles or Mac OS Software environme...

Page 12: ...time by LabVIEW RT Measurement Studio which includes LabWindows CVI tools for Visual C and tools for Visual Basic is a development suite that allows you to use ANSI C Visual C and Visual Basic to des...

Page 13: ...dresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts NI DAQ maintains a consistent software interface among its different versions so that you ca...

Page 14: ...are properly detected Unpacking Your 653X Device Your 653X device is shipped in an antistatic package to prevent electrostatic damage to the device To avoid such damage in handling the device take the...

Page 15: ...perly detected Installing the PCI DIO 32HS PCI 6534 or PCI 7030 6533 You can install a PCI DIO 32HS PCI 6534 or PCI 7030 6533 device in any available 5 V PCI expansion slot in your computer 1 Turn off...

Page 16: ...e the PXI 653X onboard DMA controller using your software PXI compliant chassis have bus arbitration for all slots 3 Remove the filler panel for the peripheral slot you have chosen 4 Touch a metal par...

Page 17: ...ut slot compatibility 1 Turn off your computer If your computer and operating system support hot insertion you may insert or remove the DAQCard 6533 at any time whether the computer is powered on or o...

Page 18: ...on to test hardware resources Warning Do not configure the 653X resources in conflict with non National Instruments devices For example do not configure two devices to have the same base address Note...

Page 19: ...Use I need to perform basic digital I O that does not need hardware timing or handshaking between the 653X and the peripheral device Unstrobed I O I want to configure the direction of each bit indivi...

Page 20: ...high Advantages include It does not require pull up resistors It is independent of the state of the DPULL line It has high current drive for both its logic high and logic low states It can drive high...

Page 21: ...receive digital patterns and waveforms at regular intervals or timed by an external TTL signal Transfer data between two devices using one of six configurable handshaking protocols Acquire digital dat...

Page 22: ...gram Using the following flowcharts as a guide create a program to perform unstrobed I O Figure 2 1 displays a flowchart for C programming using NI DAQ while Figure 2 2 shows a LabVIEW programming flo...

Page 23: ...f both sets of control timing lines are available call the DIG_In_Prt or DIG_Out_Prt function and set Port Number to 4 If both sets of control timing lines are not available use the DIG_In_Line and DI...

Page 24: ...of signals to request and acknowledge each data transfer use the handshaking I O mode Deciding the Width of Data to Transfer You can choose between a width of eight 16 or 32 bits Use the following ta...

Page 25: ...s of Chapter 3 Timing Diagrams Using the Burst Protocol The burst protocol differs from all the other handshaking protocols in that it is the only synchronous clocked protocol In addition to ACK and R...

Page 26: ...l control timing trigger lines Choosing Whether or Not to Use a Programmable Delay For all the protocols you have the option to set a programmable delay This is useful when the handshaking signals of...

Page 27: ...o retrieve the data If at any time the device runs out of space in the buffer it pauses the handshaking operation until your program clears up more buffer space You have the option to allow the device...

Page 28: ...DAQ C interface Set the ND_PATTERN_GENERATION_LOOP_ENABLED to ND_ON in the Set_DAQ_Device_Info function LabVIEW Set the Pattern Generation Loop Enable attribute to ON in the DIO Parameter VI Choosing...

Page 29: ...ing a valid ACK value before you enable the transfer on the peripheral device Similarly you can make sure the peripheral device is configured and is driving a valid REQ value before you enable the tra...

Page 30: ...control line state of the REQ and ACK lines is low If you want to change state to high use one of the three following methods Use the CPULL bias selection line and connect the CPULL pin on the I O con...

Page 31: ...shaking I O in NI DAQ Read DIG_Grp_Mode DIG_Grp_Config Read Continuous No DIG_DB_Config Yes DIG_Block_In DIG_Block_Out DIG_Block_In DIG_Block_Out Yes No Yes No Yes DIG_DB_HalfReady Is the next half bu...

Page 32: ...e 2 5 Programming Unbuffered Handshaking I O in NI DAQ DIG_Grp_Config Input DIG_Grp_Mode DIG_Grp_Status Ready DIG_In_Grp DIO_Grp_Config Done DIG_Out_Grp DIG_Grp_Status Ready Done DIG_In_Grp DIO_Grp_Co...

Page 33: ...RT DIO Start VI DIO Parameter VI DIO Clear VI Buffered Operation DIO Config VI Yes Burst Mode No No No Reverse PCLK Direction Yes Yes Finite Buffer DIO Read VI Yes Done DIO Read VI Yes No No Digital...

Page 34: ...e to eliminate or reduce the impact of the PCI bus bandwidth limitations and increase the overall transfer rate DIO Start VI DIO Parameter VI DIO Clear VI Buffered Operation DIO Config VI Yes Burst Mo...

Page 35: ...edge of a clock signal The clock signal can be generated internally by an onboard 32 bit counter set to a user specified frequency or the clock signal can be received from the REQ pin in the I O conn...

Page 36: ...he internal REQ source You can reverse the REQ polarity by using the following functions NI DAQ C interface Specify the REQ polarity in the DIG_Group_Mode function before calling the DIG_Block_PG_Conf...

Page 37: ...t and Stop Data Transfer Triggering By default data transfer starts upon a software command the Digital Buffer Control VI called by the DIO Start VI in LabVIEW and the DIG_Block_In and DIG_Block_Out f...

Page 38: ...s received before a start trigger it is ignored If the stop trigger arrives before all the pretrigger data is acquired NI DAQ returns an error Figure 2 10 Using a Start and Stop Trigger Pattern Matchi...

Page 39: ...continuously into or from computer memory or specify the number of points you want to transfer Finite Transfers For finite transfers the 653X device transfers the specified amount of data to from com...

Page 40: ...a into onboard memory and looping through this data block continuously With this option data is only transferred from computer memory to the device onboard memory once and the device outputs the same...

Page 41: ...nt bits LabVIEW Use the Digital Buffer Write VI or the Digital Buffer Read VI which are called by the DIO Read VI the DIO Write VI and the DIO Wait VI Connecting Signals Connect digital input signals...

Page 42: ...rform pattern I O Figures 2 13 and 2 14 display flowcharts for C programming using NI DAQ while Figure 2 14 shows a LabVIEW programming flowchart The boxes represent function names for the appropriate...

Page 43: ...lfReady Is the next half buffer ready DIG_DB_Transfer DIG_Block_Clear Acquisition Complete Yes Yes No No Yes No DIG_Block_In DIG_Block_Out DIG_Grp_Config DIG_Trigger_Config DIG_DB_Config DIG_Block_PG_...

Page 44: ...load Enable attribute to OFF Monitoring Line State Change Detection You can configure your 653X device to acquire data whenever the state of one or more data lines change Once the 653X device detects...

Page 45: ...ue of the entire port is acquired Figure 2 15 Change Detection Example Settings Deciding How to Start and Stop Data Transfer Triggering By default data transfer starts upon a software command the Digi...

Page 46: ...buffer Once this data is in the buffer transfer stops If the stop trigger arrives before all the pretrigger data is acquired an error will return in software Figure 2 17 Stopping Data Transfer Using a...

Page 47: ...t for pattern detection Note The mask for the pattern matching trigger is the same as the one used for change detection In other words input lines significant for the pattern matching trigger are also...

Page 48: ...uffer and stops the operation Continuous Input For continuous input the 653X device transfers input data to the computer memory buffer continuously As the device is filling the buffer call the DIG_DB_...

Page 49: ...processing time from the computer than DMA driven transfers Connecting Signals Connect digital input signals to the I O connector using the pinout diagrams Figures C 1 653X I O Connector 68 Pin Assig...

Page 50: ...NI DAQ DIG_DB_HalfReady Is the next half buffer ready DIG_DB_Transfer DIG_Block_Clear Acquisition Complete Yes Yes No No DIG_Grp_Config DIG_Trigger_Config DIG_DB_Config DIG_Block_PG_Config DIG_Block_I...

Page 51: ...National Instruments Corporation 2 33 653X User Manual Figure 2 22 Programming Change Detection for LabVIEW LabVIEW RT DIO Config VI Trigger Config VI DIO Read VI Done DIO Clear VI Yes No DIO Start V...

Page 52: ...n software both of which can lower your transfer rate For more information about transfer rates see Appendix E Optimizing Your Transfer Rates Internal REQ Signal Source The 653X can internally generat...

Page 53: ...of the REQ signal must each be 20 ns The minimum duration for a period of the REQ signal is 50 ns Note For data transfers that use a hardware start trigger there is no mandatory setup tsu or hold tim...

Page 54: ...ynchronized to the REQ edge using a flip flop Because of this synchronization flip flop there is a one REQ pulse delay after STARTRIG before the data capture begins There is a possibility of a two cyc...

Page 55: ...able 3 1 Note Whether an ACK or a REQ signal occurs first in the handshaking sequence depends on the protocol and the direction of the transfer Table 3 1 Handshaking Protocol Characteristics Protocol...

Page 56: ...LK line The 653X device asserts the ACK signal if it is ready to perform a transfer If the peripheral device also asserts the REQ signal indicating it is ready a transfer occurs on the rising edge of...

Page 57: ...both the 653X device and the peripheral device are ready and thus ACK and REQ are asserted it is not reasonable to expect data to arrive at consistent intervals If consistent intervals are an importa...

Page 58: ...output clock signal onto the PCLK line or receive an input clock signal from the PCLK line By default the PCLK line is set for input during output transfers and set for output during input transfers...

Page 59: ...a valid to PCLK 4 tdih Hold time from PCLK to input data invalid 6 Output Parameters tpc PCLK cycle time 50 7001 tpw PCLK high pulse duration tpc 2 5 tpc 2 5 tpa PCLK to ACK valid 18 tah Hold time fro...

Page 60: ...gh pulse duration 20 tpl PCLK low pulse duration 20 trs Setup time from REQ valid to PCLK falling edge 1 trh Hold time from PCLK to REQ invalid 0 Output Parameters tpa PCLK to ACK valid 22 tah Hold ti...

Page 61: ...pl PCLK low pulse duration 20 trs Setup time from REQ valid to PCLK falling edge 1 trh Hold time from PCLK to REQ invalid 0 tdis Setup time from input data valid to PCLK falling edge 0 tdih Hold time...

Page 62: ...high pulse duration tpc 2 5 tpc 2 5 tpa PCLK to ACK valid 18 tah Hold time from PCLK to ACK invalid 3 tpdo PCLK to output data valid 28 tdoh Hold time from PCLK to output data invalid 4 tdis Setup ti...

Page 63: ...REQ edge before reading the data For output after writing the data the 653X device latches data out of the I O connector on the active REQ edge The active edge of the REQ is determined rising or fall...

Page 64: ...ulation Input Handshaking Sequence Reference Point Action Steps 1 The 653X device asserts the ACK signal when ready to accept data 2 The peripheral device can then strobe data into the 653X device by...

Page 65: ...om Figure 3 10 8255 Emulation Input State Machine Wait For Space Wait For REQ Programmable Delay Wait For REQ When REQ Unasserted Latch Input Data When 6533 Device has space for data input data Clear...

Page 66: ...rising edge of the ACK signal or any time in between before the next rising edge on REQ 4 The REQ signal edge in step 2 causes the ACK signal to return to deassert 5 The rising REQ signal edge enables...

Page 67: ...Figure 3 12 8255 Emulation Output State Machine Wait For Data Wait For REQ Programmable Delay Wait For REQ When REQ Unasserted When 6533 Device has data to output output data When REQ Asserted Initial...

Page 68: ...edge to REQ rising edge 0 tdir Input data valid to REQ rising edge 0 trdi REQ rising edge to input data invalid 10 Output Parameters taa ACK high duration 100 tr a REQ falling edge to ACK rising edge...

Page 69: ...erts REQ the peripheral may either pulse REQ or hold REQ high until the first ACK occurs If the peripheral pulses REQ make sure to start the transfer on the 653X device before the pulse occurs to avoi...

Page 70: ...State Machine Wait For Space Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted Clear ACK When 6533 Device has space for data input data When REQ Unasserted Initial Sta...

Page 71: ...atching 0 trdi Input data hold from REQ active with REQ edge latching 10 tdir 2 Input data setup to REQ with REQ edge latching disabled 0 tadi Input data hold from ACK with REQ edge latching disabled...

Page 72: ...put it drives the data onto the data lines and then asserts ACK ACK stays asserted indicating the 653X device is ready until the active going REQ edge occurs 2 The peripheral device responds with an a...

Page 73: ...For Data Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted Clear ACK When 6533 Device has data to output output data When REQ Unasserted Initial State ACK Cleared Send...

Page 74: ...um Maximum Input Parameters trr REQ pulse width 75 tr r REQ inactive duration 75 tar ACK to next REQ 0 Output Parameters taa ACK pulse width 225 tra REQ to ACK inactive 100 200 tr do REQ inactive to n...

Page 75: ...ates that the 653X device or peripheral device is ready for a transfer Long pulse protocol This is a variant of the leading edge protocol with the additional option of using a data settling delay If y...

Page 76: ...o receive data 2 After receiving the trailing edge of the ACK pulse the peripheral device can strobe data into the 653X device and pulse the REQ 3 The 653X device sends another ACK pulse when ready fo...

Page 77: ...nput Parameters trr REQ pulse width 75 tr r REQ inactive duration 75 tdir Input data setup to REQ inactive with REQ edge latching 0 tr di Input data hold from REQ inactive with REQ edge latching 10 td...

Page 78: ...peripheral device responds with a REQ pulse The trailing edge of the REQ pulse deasserts the ACK signal and requests additional data ACK REQ 2 1 ACK and REQ are shown as active high Steps 1 2 are rep...

Page 79: ...arameters trr REQ pulse width 75 tr r REQ inactive duration 75 ta r ACK inactive to next REQ inactive 0 Output Parameters taa ACK pulse width 2251 2752 tr do 1 REQ inactive to new output data with REQ...

Page 80: ...make sure to start the transfer on the 653X device before the pulse occurs to avoid missing the pulse 1 The 653X device sends an ACK pulse when it is ready to receive data The ACK pulse width is fixed...

Page 81: ...t For Space Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted When 6533 Device has space for data input data Clear ACK Pulse When REQ Unasserted Initial State ACK Clear...

Page 82: ...REQ edge latching 0 trdi Input data hold from REQ active with REQ edge latching 10 tdir 2 Input data setup to REQ with REQ edge latching disabled 0 tadi Input data hold from ACK with REQ edge latchin...

Page 83: ...sserted 1 The 653X device sends the ACK pulse after driving output data to indicate that it has new valid output data The ACK pulse width is fixed assuming the peripheral device has deasserted the REQ...

Page 84: ...hine Wait For Data Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted Clear ACK Pulse When REQ Unasserted Initial State ACK Cleared When 653X Device has data to output o...

Page 85: ...Parameters trr REQ pulse width 75 tr r REQ inactive duration 75 tar ACK to next REQ 0 Output Parameters taa ACK pulse width 125 tr a REQ inactive to ACK inactive 150 tr do REQ inactive to new output d...

Page 86: ...e pulse occurs to avoid missing the pulse 1 The 653X device asserts an ACK signal when it is ready to receive data assuming the peripheral device has deasserted the REQ signal Otherwise the ACK signal...

Page 87: ...For Space Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted When 6533 Device has space for data input data Clear ACK Pulse When REQ Unasserted Initial State ACK Cleare...

Page 88: ...REQ edge latching 0 trdi Input data hold from REQ active with REQ edge latching 10 tdir 2 Input data setup to REQ with REQ edge latching disabled 0 tadi Input data hold from ACK with REQ edge latchin...

Page 89: ...asserted 1 The 653X device sends an ACK pulse with programmable width to indicate that it has data to output Assuming the peripheral device has deasserted the REQ signal Otherwise the ACK signal remai...

Page 90: ...ine Wait For Data Wait For REQ Programmable Delay Programmable Delay Wait For REQ When REQ Asserted When 6533 Device has data to output output data Clear ACK Pulse When REQ Unasserted Initial State AC...

Page 91: ...um Maximum Input Parameters trr REQ pulse width 75 tr r REQ inactive duration 75 tar ACK to next REQ 0 Output Parameters taa ACK pulse width 1251 tr do REQ inactive to new output data with REQ edge la...

Page 92: ...els 32 input output 4 dedicated output and control 4 dedicated input and status Compatibility TTL CMOS standard or wired OR Hysteresis 500 mV Digital logic levels Level Min Max Input low voltage 0 V 0...

Page 93: ...two 32 MB modules on each 6534 device PCI PXI 7030 6533 16 S PCI DIO 32HS 16 S PXI 6533 16 S Input high current for control lines Vin 2 4 V CPULL high CPULL low 200 A 1 4 mA Input low current for CPU...

Page 94: ...mpatibility TTL CMOS Trigger types Rising or falling edge or digital pattern Pulse width for edge triggers min 10 ns Pattern trigger detection capabilities Detect pattern match or mismatch on user sel...

Page 95: ...CMCIA 3 4 by 2 1 in AT DIO 32HS PCI 653X 6 9 by 4 2 in PXI 653X 6 4 by 3 9 in I O connector PCI DIO 32HS PXI 6533 AT DIO 32HS PCI 6534 and PXI 6534 68 pin male SCSI II type DAQCard 6533 for PCMCIA 68...

Page 96: ...tional random vibration PXI only 5 to 500 Hz 2 5 grms 3 axes Note Random vibration profiles were developed in accordance with MIL T 28800E and MIL STD 810E Method 514 Test levels exceed those recommen...

Page 97: ...s not include these sub buses Your PXI 653X device will work in any standard CompactPCI chassis adhering to the PICMG CompactPCI 2 0 R2 1 document PXI specific features are implemented on the J2 conne...

Page 98: ...your data transfer when using the handshaking and pattern I O modes The direction and function of each signal varies depending on the mode of operation as shown in Table C 1 Table C 1 Control Signals...

Page 99: ...nal connections Figure C 1 653X I O Connector 68 Pin Assignments 5 V REQ1 ACK1 STARTTRIG1 STOPTRIG1 PCLK1 PCLK2 STOPTRIG2 ACK2 STARTTRIG2 REQ2 DIOA0 GND DIOA3 DIOA4 GND DIOA7 DIOB0 DIOB1 GND RGND GND...

Page 100: ...rm handshaking I O between two 653X devices using an SH 68 68 D1 cable Use Table C 2 to find the accessories designed for connecting signals to your 653X device Signal Descriptions Use Table C 3 to fi...

Page 101: ...hese lines Unstrobed I O Option to use the ACK 1 2 lines as extra general purpose output lines OUT 3 4 4 7 STOPTRIG 1 2 Control Group 1 and group 2 stop triggers Handshaking I O Not used Pattern I O U...

Page 102: ...ll down selection Input signal that selects whether the 653X device pulls the data lines DIOA DIOB DIOC and DIOD up or down when undriven If you connect DPULL to 5 V on the external terminal connector...

Page 103: ...4 DIOB0 DIOB7 DIOB5 DIOA7 DIOA1 DIOA0 DIOA4 REQ1 PCLK1 OUT1 STOPTRIG1 IN1 ACK1 GND GND GND GND GND DIOC6 DIOC2 DIOC3 DIOC5 DIOD2 DIOD6 DIOD3 DIOD1 DIOB1 DIOB6 DIOB2 DIOA3 DIOA2 DIOA6 GND DIOB3 DIOA5 G...

Page 104: ...including Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 and 68 pin screw terminals RTSI bus cables for AT and PCI devices SCXI modules and accessories tha...

Page 105: ...and how the hardware works in your 653X device Block Diagrams Figure D 1 AT DIO 32HS Block Diagram DAQ DIO Counters and Timers DMA Interrupt Requests Handshaking and Control Data Latches and Drivers D...

Page 106: ...CIA Block Diagram DAQ DIO Counters and Timers DMA Interrupt Requests Handshaking and Control Data Latches and Drivers Data Lines Data Lines 32 16 PCMCIA Interface PCMCIA I O Channel Control Lines 8 I...

Page 107: ...6533 Block Diagram DAQ DIO Counters and Timers DMA Interrupt Requests Handshaking and Control Data Latches and Drivers Data Lines Data Lines 32 32 MITE PCI Interface PCI I O Channel EEPROM RTSI PXI T...

Page 108: ...FOs Bus Interface DMA IRQ Counter and Timers Clock Selection DAQ DIO Bus Interface SCARAB Interface SCARAB Interface FPGA MITE Interface DMA IRQ Handshaking and Control RTSI Interface Data Lines 32 I...

Page 109: ...und pull down Caution Do not connect CPULL DPULL or any other line directly to an external power supply while the 653X device is powered off Doing this may prevent your computer from booting For examp...

Page 110: ...hes a low inductance uniform transmission line For more information about this cable and other accessories see Appendix C Connecting Signals with Accessories Tip Cables that do not meet the above requ...

Page 111: ...V connection through a long wire back to the 5 V pin of the 653X device add a capacitor to your termination circuit to stabilize the 5 V connection near the Schottky diodes One suitable Schottky diod...

Page 112: ...or slew rate of the 653X device or the characteristic impedance of the SH6868 D1 cable However the following information might be helpful I O buffers The DIO 32HS uses 24 mA rate controlled TTL level...

Page 113: ...each other Do not run signal lines through conduits that also contain power lines How Much Current Can I Sink or Source Make sure the sink current does not exceed 24 mA at 0 4 V to guarantee that TTL...

Page 114: ...Instruments PXI modules that provide a connection to these pins can be connected together by software This feature is available only when the PXI 653X is used in a PXI compatible chassis It is not sup...

Page 115: ...igger bus line You can drive output control signals onto the bus and receive input control signals from the bus Figure D 6 shows the signal connection scheme Note If you configure a signal to be recei...

Page 116: ...r application software The maximum sustainable transfer rate is always lower than the peak transfer rate The average bus bandwidth from highest to lowest is in the following order PCI PXI 6534 PCI PXI...

Page 117: ...than interrupt driven transfers especially for pattern I O Refer to Table E 2 to determine whether your device supports DMA transfers If DMA transfers are available the software will use it by defaul...

Page 118: ...ion then sample size is one byte Sixteen bits is two bytes and 32 bits is four bytes To convert from MS s to MB s use the following formula where sample size can be one two or four bytes For example 1...

Page 119: ...IO 32HS Benchmark Results Mode Benchmark Rate MS s 8 Bit 16 Bit 32 Bit Pattern I O Single Shot Input 1 67 87 83 Output 1 47 74 38 Pattern I O Continuous Input 1 67 80 31 Pattern I O Continuous Retrans...

Page 120: ...Protocol Continuous Retransmit Output 19 92 19 58 18 54 Table E 5 PXI 6533 Benchmark Results Mode Benchmark Rate MS s 8 Bit 16 Bit 32 Bit Pattern I O Single Shot Input 10 6 67 5 Output 5 2 5 2 5 Patt...

Page 121: ...6533 for PCMCIA Benchmark Results Mode Benchmark Rate MS s 8 Bit 16 Bit 32 Bit Pattern I O Single Shot Input 0 12 11 10 Output 0 12 12 10 Pattern I O Continuous Input 0 12 11 10 Pattern I O Continuous...

Page 122: ...hmarks made using buffer retransmitted onboard memory Table E 8 PXI 6534 Benchmark Results Mode Benchmark Rate MS s 8 Bit 16 Bit 32 Bit Pattern I O Single Shot Input 20 20 20 Output 20 20 20 Pattern I...

Page 123: ...e operating system running on LabVIEW RT Table E 9 PCI 7030 6533 Benchmark Results Mode Benchmark Rate MS s 8 Bit 16 Bit 32 Bit Pattern I O Single Shot Input 1 82 95 49 Output 1 82 91 47 Pattern I O C...

Page 124: ...Corporation E 9 653X User Manual Pattern I O Continuous Retransmit Output 2 50 1 25 1 25 Burst Protocol Continuous Input 19 98 19 97 19 97 Output 19 97 17 72 8 60 Table E 10 PCI 7030 6533 Benchmark R...

Page 125: ...latest example programs system configurators tutorials technical news as well as a community of developers ready to share their own techniques Customer Education National Instruments provides a numbe...

Page 126: ...s from the Worldwide Offices section of ni com Branch office web sites provide up to date contact information support phone numbers e mail addresses and current events If you have searched the technic...

Page 127: ...Meaning Value k kilo 103 micro 10 6 m milli 10 3 M mega 106 n nano 10 9 Numbers Symbols degrees negative of or minus less than greater than less than or equal to greater than or equal to ohms per per...

Page 128: ...the property of a function that begins an operation and returns prior to the completion or termination of the operation B b bits B bytes bidirectional data lines data lines that can be programmatical...

Page 129: ...shaking I O and pattern I O There are four control signals in your 653X device ACK STARTTRIG REQ STOPTRIG and PCLK counter timer a circuit that counts external pulses or clock pulses timing CPULL A us...

Page 130: ...connect the line to 5 VDC pull up or connect the line to ground pull down F FIFO First In First Out memory buffer the first data stored is the first data sent to the acceptor FIFOs are often used on D...

Page 131: ...ansferred only when both the 653X and the peripheral device are ready I interrupt a computer signal indicating that the CPU should suspend its current task to service a designated activity I O Input O...

Page 132: ...ansion bus architecture originally developed by Intel to replace ISA and EISA It has achieved widespread acceptance as a standard for PCs and workstations it offers a theoretical maximum transfer rate...

Page 133: ...r time REQ Request Handshaking signal generated by the peripheral device indicating it is ready In some transfer modes the 653X device can internally generate a REQ signal The REQ signal with a bar ab...

Page 134: ...T transfer rate the rate measured in bytes s at which data is moved from source to destination after software initialization and set up operations the maximum rate at which the hardware can operate t...

Page 135: ...y National Instruments Corporation G 9 653X User Manual W wired OR output driver that drives its output pin to 0 V for logic low but tri states the pin puts the pin in the high impedance state for log...

Page 136: ...e figure 3 13 input state machine figure 3 14 output handshaking sequence figure 3 15 output state machine figure 3 16 output timing diagram figure 3 17 overview 3 12 to 3 13 burst input timing diagra...

Page 137: ...col 3 12 AT DIO 32HS benchmark results table E 4 block diagram D 1 installation 1 7 to 1 8 support for DMA transfers table E 2 B benchmark results See optimizing transfer rates block diagrams AT DIO 3...

Page 138: ...2 30 handshaking I O 2 9 to 2 10 continuous input 2 9 continuous output 2 9 to 2 10 DMA or interrupt transfers 2 10 finite 2 9 pattern I O 2 21 to 2 22 continuous input 2 21 to 2 22 continuous output...

Page 139: ...gnal description table C 5 H handshaking I O 2 6 to 2 17 See also handshaking I O timing diagrams ACK REQ signal polarity 2 8 connecting signals 2 10 to 2 11 continuous or finite data transfer 2 9 to...

Page 140: ...ut state machine figure 3 22 output timing diagram figure 3 23 long pulse protocol 3 35 to 3 40 input handshaking sequence figure 3 35 input state machine figure 3 36 input timing diagram figure 3 37...

Page 141: ...e 3 34 level ACK handshaking protocol 3 18 to 3 23 comparison of protocols table 3 4 to 3 5 input handshaking sequence figure 3 18 input state machine figure 3 19 input timing diagram figure 3 20 maxi...

Page 142: ...ingle buffer in NI DAQ 2 24 REQ polarity 2 18 specifications A 3 timing diagrams 3 1 to 3 3 external REQ signal source 3 2 to 3 3 internal REQ signal source 3 1 to 3 2 transfer direction 2 18 transfer...

Page 143: ...ge detection in NI DAQ figure 2 32 handshaking I O 2 12 to 2 17 buffered handshaking I O in NI DAQ figure 2 13 handshaking input in LabVIEW LabVIEW RT figure 2 15 handshaking output in LabVIEW LabVIEW...

Page 144: ...m figure 3 23 long pulse protocol input handshaking sequence figure 3 35 input state machine figure 3 36 input timing diagram figure 3 37 output handshaking sequence figure 3 38 output state machine f...

Page 145: ...r available at I O connector A 4 power requirement A 4 triggers RTSI triggers PCI PXI AT A 3 start and stop triggers A 3 standard output unstrobed I O 2 2 start and stop trigger change detection 2 28...

Page 146: ...te machine figure 3 25 input timing diagram figure 3 26 maximum transfer rate table E 3 output state machine figure 3 27 output timing diagram figure 3 28 transferring data See data transfer trigger b...

Page 147: ...Index 653X User Manual I 12 ni com W waveforms See pattern I O Web support from National Instruments F 1 wired OR output unstrobed I O 2 2 to 2 3 Worldwide technical support F 2...

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