National Instruments NI 6115 User Manual Download

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National Instruments Corporation

3-1

Hardware Overview

This chapter presents an overview of the hardware functions on the
NI 6115/6120. Figures 3-1 and 3-2 provide block diagrams for the NI 6115
and NI 6120, respectively.

Figure 3-1.

NI 6115 Block Diagram

Timing

PFI / Trigger

I/O Connector

RTSI Bus

STC Digital I/O (8)

EEPROM

CH0
Amplifier
–

Calibration

Mux

AI CH0

Mux

Analog
Trigger

Circuitry

Trigger Level

DACs

Trigger

Calibration

DACs

DAC1

DAQ - STC

Analog Input

Timing/Control

Analog Output
Timing/Control

Digital I/O

Trigger

Counter/

Timing I/O

RTSI Bus

Interface

DMA/IRQ

Bus

Interface

DAC

FIFO

Address/Data

Control

Data (32)

Analog

Input

Control

EEPROM

Control

DMA

Interface

FPGA

DAQ-STC

Bus

Interface

Analog
Output
Control

I/O

Bus

Interface

IRQ
DMA

Mini

MITE

Generic

Bus

Interface

PCI
Bus

Interface

CH0+

CH0–

CH1
Amplifier
–

AI CH1

Mux

CH1

Latch

CH1+

CH1–

CH2
Amplifier
–

AI CH2

Mux

CH2

Latch

CH2+

CH2–

CH3
Amplifier
–

AI CH3

Mux

CH3

Latch

CH3+

CH3–

AI Control

Data (16)

ADC

FIFO

Data (12)

DIO

FIFO

DIO

Control

AO Control

FPGA Digital I/O (8)

Digital I/O (8)

PXI/PCI Bus

DAC0

Anti-

Aliasing

Filter

CH0

12-Bit

ADC

Anti-

Aliasing

Filter

CH1

12-Bit

ADC

Anti-

Aliasing

Filter

CH2

12-Bit

ADC

Anti-

Aliasing

Filter

CH3

12-Bit

ADC

DIO

MUX

CH0

Latch

Data (32)

Summary of Contents for NI 6115

Page 1: ...DAQ NI 6115 6120 User Manual Multifunction I O Devices for PCI PXI CompactPCI Bus Computers NI 6115 6120 User Manual August 2002 Edition Part Number 322812B 01 ...

Page 2: ...48 14 24 24 Germany 089 741 31 30 Greece 01 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 22 3390 150 Portugal 210 311 210 Russia 095 238 7139 Singapore 65 6 226 5886 Slovenia 3 425 4200 South Africa 11 80...

Page 3: ...tion operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing...

Page 4: ...uments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial enviro...

Page 5: ...includes a DoC for most every hardware product except for those bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate pr...

Page 6: ...tional Instruments ADE Software 1 5 Optional Equipment 1 6 Custom Cabling 1 6 Unpacking 1 7 Safety Information 1 8 Chapter 2 Installing and Configuring the NI 6115 6120 Installing the Software 2 1 Installing the Hardware 2 1 Configuring the Device 2 3 Chapter 3 Hardware Overview Analog Input 3 2 Input Mode 3 2 Input Polarity and Input Range 3 3 Considerations for Selecting Input Ranges 3 4 Input C...

Page 7: ...12 Working Voltage Range 4 13 Connecting Analog Output Signals 4 14 Connecting Digital I O Signals 4 15 Correlating DIO Signal Connections 4 16 Power Connections 4 18 Connecting Timing Signals 4 18 Programmable Function Input Connections 4 20 DAQ Timing Connections 4 20 TRIG1 Signal 4 21 TRIG2 Signal 4 22 STARTSCAN Signal 4 24 CONVERT Signal 4 26 AIGATE Signal 4 27 SISOURCE Signal 4 27 SCANCLK Sig...

Page 8: ..._DOWN Signal 4 37 FREQ_OUT Signal 4 38 Field Wiring Considerations 4 39 Chapter 5 Calibration Loading Stored Calibration Constants 5 1 Self Calibration 5 2 External Calibration 5 2 Appendix A Specifications Appendix B Common Questions Appendix C Technical Support and Professional Services Glossary Index ...

Page 9: ...gle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO 3 0 The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box The symbol indicates ...

Page 10: ...fers to any device in the NI 6115 6120 family PCI Peripheral Component Interconnect PCI is a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA Platform Text in this font denotes a specific platform and indicates that the text following it applies only to that platform PXI A rugged open system for modular instrumentation based on CompactPCI with speci...

Page 11: ...e documentation before you configure the hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making the connections Related Documentation The following documents contain information you may find h...

Page 12: ...le by the NI MITE bus interface chip that connects the device to the PXI or PCI I O bus The MITE implements the PCI Local Bus Specification so that you can configure all the interrupts and base memory addresses with software The NI 6115 6120 uses the NI data acquisition system timing controller DAQ STC for time related functions The DAQ STC consists of three timing groups that control AI AO and ge...

Page 13: ...asic plug in device functions For example the RTSI interface on the NI PXI 6115 6120 is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices w...

Page 14: ...6115 NI PXI 6115 NI PCI 6120 NI PXI 6120 NI 6115 6120 User Manual NI DAQ for PC compatibles Optional One of the following software packages and documentation LabVIEW Windows Measurement Studio Windows VI Logger Windows Table 1 1 NI PXI 6115 6120 J2 Pin Assignment NI PXI 6115 6120 Signal PXI Pin Name PXI J2 Pin Number RTSI 0 5 PXI Trigger 0 5 B16 A16 A17 A18 B18 C18 RTSI 6 Star D17 RTSI Clock PXI T...

Page 15: ...nctions that you can call from the ADE These functions allow you to use all the features of the device NI DAQ carries out many of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you are using ...

Page 16: ...for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW LabWindows CVI is a complete ANSI C ADE that features an interactive user interface code generation tools and the LabWindows CVI Data Acquisition and Easy I O libraries Measurement Studio which includes tools for Visual C and tools for Visual Basic is a development suite that allows you to design test and measurement...

Page 17: ... the development time for your data acquisition and control application Optional Equipment NI offers a variety of products to use with the NI 6115 6120 including cables connector blocks and other accessories as follows Shielded cables and cable assemblies Connector blocks shielded 50 and 68 pin screw terminals RTSI bus cables PCI only Low channel count signal conditioning modules devices and acces...

Page 18: ...r Honda backshell Unpacking The NI 6115 6120 is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge ESD can damage several components on the device Caution Never touch the exposed pins of connectors To avoid such damage when handling the device take the following precautions Ground yourself using a grounding strap or by holding a grounded object T...

Page 19: ...lid liquid or gaseous state that can reduce dielectric strength or surface resistivity The following is a description of pollution degrees Pollution Degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence Pollution Degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation ...

Page 20: ...ar equipment Installation Category III is for measurements performed in the building installation This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation Examples of Installation Category III include measurements on distribution circuits and circuit breakers Other examples of Installation Category III are wiring including cables bus...

Page 21: ...Chapter 1 Introduction NI 6115 6120 User Manual 1 10 ni com Below is a diagram of a sample installation ...

Page 22: ...ntical to the pinout for the NI 6115 6120 Note It is important to install NI DAQ before installing the NI 6115 6120 to ensure that the device is properly detected Installing the Hardware You can install the NI 6115 6120 in any available expansion slot in the computer However to achieve best noise performance leave as much room as possible between the NI 6115 6120 and other devices and hardware The...

Page 23: ... fully insert the device into the chassis 8 Screw the front panel of the NI PXI 6115 6120 to the front panel mounting rail of the system 9 Visually verify the installation Make sure the device is not touching other devices or components and is fully inserted in the slot 10 Plug in and power on the computer The NI PXI 6115 6120 is now installed You are now ready to configure the hardware and softwa...

Page 24: ...ns with no user interaction Bus related configuration includes setting the device base memory address and interrupt channel The NI PXI 6115 6120 is fully compatible with the industry standard PXI Specification Revision 2 0 This allows the PXI CompactPCI system to automatically perform all bus related configurations with no user interaction Bus related configuration includes setting the device base...

Page 25: ... Trigger Counter Timing I O RTSI Bus Interface DMA IRQ Bus Interface DAC FIFO Address Data Control Data 32 Analog Input Control EEPROM Control DMA Interface FPGA DAQ STC Bus Interface Analog Output Control I O Bus Interface IRQ DMA Mini MITE Generic Bus Interface PCI Bus Interface CH0 CH0 CH1 Amplifier AI CH1 Mux CH1 Latch CH1 CH1 CH2 Amplifier AI CH2 Mux CH2 Latch CH2 CH2 CH3 Amplifier AI CH3 Mux...

Page 26: ...EPROM CH0 Amplifier Calibration Mux AI CH0 Mux Analog Trigger Circuitry 2 Trigger Level DACs Trigger Calibration DACs DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA IRQ Bus Interface DAC FIFO Address Data Control Data 32 Analog Input Control EEPROM Control DMA Interface FPGA DAQ STC Bus Interface Analog Output Con...

Page 27: ...n accommodate It has ranges of 42 V 20 V 10 V 5 V 2 V 1 V 500 mV and 200 mV and is suited for a wide variety of signal levels By choosing the optimal gain setting you can maximize usage of the dynamic range of the ADC which effectively increases input signal resolution Table 3 1 shows the overall input range and precision according to the gain used Caution The NI 6115 6120 is not designed for inpu...

Page 28: ...ffset for the input amplifier and amplify only the AC component This configuration effectively uses the dynamic range of the ADC The input impedance for the programmable gain instrumentation amplifier PGIA channels is 1 MΩ for ranges 10 V and 10 kΩ for ranges 10 V This configuration provides an AC coupled corner frequency of 2 34 Hz for ranges 10 V and 234 Hz for ranges 10 V Table 3 1 Input Range ...

Page 29: ...a direct analog input from the PFI0 TRIG1 pin on the I O connector or a post gain signal from the output of the PGIA on any of the channels as shown in Figure 3 3 The trigger level range for the direct analog channel is 10 V with a resolution of 78 mV for the NI 6115 and 4 88 mV for the NI 6120 The input impedance for the direct analog channel is 10 kΩ When this direct analog channel is configured...

Page 30: ...ghValue is unused Figure 3 4 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue as shown in Figure 3 5 LowValue is unused PGIA Analog Input CH0 ADC ADC ADC DAQ STC Analog Trigger Circuit Mux PGIA Analog Input CH1 PGIA Analog Input CH2 PGIA Analog Input CH3 ADC PFI0 TRIG1 Digital Data AC Couple 1...

Page 31: ...gnal value is between the lowValue and the highValue as Figure 3 6 shows Figure 3 6 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue as Figure 3 7 shows Figure 3 7 High Hysteresis Analog Triggering Mode highValue Trigger highValue Trigger lowValue highVal...

Page 32: ... outputs whenever the AI signal crosses a specific threshold Antialiasing Filters Each AI channel on the NI 6115 6120 is equipped with a programmable antialaising Bessel filter On the NI 6115 you can program the filters to provide a third order 50 kHz lowpass filter a third order 500 kHz lowpass filter or a pass through mode with no filtering On the NI 6120 you can program the filters to provide a...

Page 33: ... PLL circuitry consists of a voltage controlled crystal oscillator VCXO with a tuning range of 50 ppm The VCXO generates the 60 MHz master clock used onboard the NI PXI 6115 6120 The PLL locks to the 10 MHz oscillator line on the PXI backplane bus A phase comparator running at 1 MHz compares the PXI Bus and VCXO clock The loop filter then processes the error signal and outputs a control voltage fo...

Page 34: ...re connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals GPCTR0_UP_DOWN and GPCTR1_UP_DOWN are input only and do not affect the operation of the DIO lines Timing Signal Routing The DAQ STC provides a flexible interface for connecting timing signals to other devices or external circuitry The NI 6115 6120 us...

Page 35: ...hows that STARTSCAN can be generated from a number of sources including the external signals RTSI 0 6 and PFI 0 9 and the internal signals Scan Interval Counter TC and GPCTR0_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Connecting Signals RTSI Trigger 0 6...

Page 36: ...general purpose signals at the I O connector The NI 6115 6120 can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or...

Page 37: ...SI 6 connects to the PXI Star Trigger line allowing the NI 6115 6120 to receive triggers from any Star Trigger controller plugged into slot 2 of the chassis For more information on the Star Trigger refer to the PXI Specification Revision 2 0 Figure 3 12 PCI RTSI Bus Signal Connection RTSI Bus Connector Clock DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN A...

Page 38: ...nals section of Chapter 4 Connecting Signals for a description of the signals shown in Figures 3 12 and 3 13 PXI Bus Connector PXI Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURSE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz RTSI Switch Switch PXI Trigger 0 5 6 PXI Star 6 ...

Page 39: ...ts Caution Connections that exceed any of the maximum ratings of input or output signals on the NI 6115 6120 can damage the device and the computer NI is not liable for any damage resulting from such signal connections The Protection column of Tables 4 3 4 4 and 4 5 show the maximum input ratings for each signal Table 4 1 I O Connector Details Device with I O Connector Number of Pins Cable for Con...

Page 40: ...11 10 9 8 7 6 5 4 3 2 1 ACH0 ACH1 ACH1GND ACH2 ACH3 ACH3GND NC NC NC NC NC NC DAC0OUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 5V OUTPUT DGND DGND PFI0 TRIG1 PFI1 TRIG2 DGND 5V OUTPUT DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTR0_GATE GPCTR0_OUT FREQ_OUT ACH0 ACH0GND ACH1 ACH2 ACH2GND ACH3 NC NC NC NC NC NC NC AOGND AOGND DGND DIO0 DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFI3 GPCTR...

Page 41: ...hannel 0 Output This pin supplies the voltage output of AO channel 0 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of AO channel 1 AOGND Analog Output Ground The AO voltages are referenced to this node DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply DIO 0 7 DGND Input Output Digital I O...

Page 42: ... GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is a PFI As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input Output PFI4 Counter 1 Gate As an input this is a PFI As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the gener...

Page 43: ...put FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output 1 The GPCTR0_OUT acts as an input when using external clock mode with correlated DIO Table 4 3 Analog I O Signal Summary for the NI 6115 Signal Name Signal Typeand Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH 0 3 AI 1 MΩ in parallel with 100 pF1...

Page 44: ...hort circuit to ground 5 at 10 5 at 10 1 Applies to range 10 V impedance refers to ACH 0 3 2 Applies to range 10 V impedance refers to ACH 0 3 Table 4 5 Digital I O Signal Summary Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias VCC DO 0 1 Ω Short circuit to ground 1 A DIO 0 7 DIO VCC 0 5 13 at VCC 0 4 24 at 0 4 1 1 ...

Page 45: ...t VCC 0 4 5 at 0 4 1 5 50 kΩ pu PFI4 GPCTR1_GATE DIO VCC 0 5 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR1_OUT DO 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ pu PFI5 UPDATE DIO VCC 0 5 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ pu PFI6 WFTRIG DIO VCC 0 5 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ pu PFI7 STARTSCAN DIO VCC 0 5 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ pu PFI8 GPCTR0_SOURCE DIO VCC 0 5 3 5 at VCC 0 4 5 at 0 4 1 5 50 kΩ ...

Page 46: ...typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Connecting Analog Input Signals The NI ...

Page 47: ...ource to a channel on the NI 6115 and NI 6120 respectively Figure 4 2 Pseudodifferential Input Connections on the NI 6115 for Ground Referenced Signals Vm ACH0 Connections Shown PGIA 100 pf 10 nf Ground Referenced Signal Source Common Mode Noise and Ground Potential AC Coupling 1 M Instrumentation Amplifier I O Connector ACH0GND ACH0 ACH0 Measured Voltage 10 kΩ 40 pf for ranges 10 V Vs Vcm Common ...

Page 48: ...s both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Vcm in Figures 4 2 and 4 3 Vm 100 pF 1 M 50 Ω 0 1 µF High Frequency Common Mode Choke ACH0 ACH0 ACH0GND PGIA Instrumentation Amplifier 10 kΩ 40 pf for ranges 10 V Ground Referenced Signal Source AC Coupling Common Mode Noise and Ground Potential Measured Voltage V...

Page 49: ...gnal source to a channel on the NI 6115 and NI 6120 respectively Figure 4 4 Differential Input Connections on the NI 6115 for Nonreferenced Signals ACH0 Connections Shown PGIA 1 M 100 pf 10 nf Bias Resistor see text AC Coupling Vm I O Connector Bias Current Return Paths Floating Signal Source Instrumentation Amplifier Measured Voltage ACH0GND ACH0 ACH0 10 kΩ 40 pf for ranges 10 V Vs Common Mode Ch...

Page 50: ...0GND This connection gives a slight measurement error due to the voltage divider formed with the output impedance of the floating source but it also gives a more balanced input for better common mode rejection Common Mode Signal Rejection Considerations Figures 4 2 and 4 3 show connections for signal sources that are already referenced to some ground point with respect to the NI 6115 6120 In theor...

Page 51: ...ignals of interest while rejecting common mode signals as long as the following three conditions are met 1 The common mode voltage Vcm which is equivalent to subtracting ACH 0 3 GND from ACH 0 3 and which is shown in Figure 4 2 must be less than 2 5 V This Vcm is a constant for all range selections 2 The signal voltage Vs which is equivalent to subtracting ACH 0 3 from ACH 0 3 and which is shown i...

Page 52: ... output signal for AO channel 0 DAC1OUT is the voltage output signal for AO channel 1 AOGND is the ground reference signal for the AO channels AOGND is a hard ground Figure 4 6 shows how to connect AO signals to the NI 6115 6120 Figure 4 6 Analog Output Connections NI 6115 6120 Analog Output Channels Channel 0 DAC0OUT AOGND DAC1OUT VOUT 0 VOUT 1 Load Load Channel 1 ...

Page 53: ...DIO port You can program groups of individual lines to be inputs or outputs Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI 6115 6120 and the computer NI is not liable for any damage resulting from such signal connections Figure 4 7 shows signal connections for three typical DIO applications Figure 4 7 Digital I O Connections 5 V LED TTL Signal 5...

Page 54: ...ck source AI Scan Start AO Update GPCTR RTSI 0 5 External Clock Notes To use either of the GPCTR signals or the external clock to clock DIO operations you must use one RTSI 0 5 pin To use an external clock for correlated DIO the clock must have input on the Counter 0 output pin GPCTR0_OUT In this case be sure that this counter is not used in any other operation The following timing diagrams illust...

Page 55: ...ion 4 17 NI 6115 6120 User Manual Figure 4 8 Clock Signal Driving DI and DO Signals Figure 4 9 shows a DIO operation driven by the AO Update signal on its rising edge Figure 4 9 Rising Edge AO Update Signal Driving a DIO Signal CLK DI 7 4 DO 3 0 AO Update DIO ...

Page 56: ... other device Doing so can damage the NI 6115 6120 and the computer NI is not liable for damage resulting from such connections Connecting Timing Signals Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI 6115 6120 and the computer NI is not liable for any damage resulting from such signal connections All external control over the timing of the NI 6...

Page 57: ...ration signals and the General Purpose Timing Signal Connections section later in this chapter explains the general purpose timing signals All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 11 which shows how to connect an external TRIG1 source and an external STARTSCAN source to two PFI pins on the NI 6115 6120 Figure 4 11 Timing I O Connections DGND ...

Page 58: ... polarity selection for any of the timing signals but the edge or level detection depends upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This setting applies for both rising edge and falling edge polarity settings...

Page 59: ...tion TRIG1 Signal Any PFI pin can receive as an input the TRIG1 signal which is available as an output on the PFI0 TRIG1 pin Refer to Figures 4 12 and 4 13 for the relationship of TRIG1 to the DAQ sequence As an input TRIG1 is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected ...

Page 60: ...5 TRIG1 Output Signal Timing The device also uses TRIG1 to initiate pretriggered DAQ operations In most pretriggered applications TRIG1 is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can receive as an input the TRIG2 signal which is available as an output on t...

Page 61: ...serted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number of scans and the acquisition stops This mode acquires data both before and after receiving TRIG2 As an output TRIG2 reflects the posttrigger in a pretriggered DAQ sequence even if another PFI is externally triggering the acquisition TRIG2 is not used in posttriggere...

Page 62: ...rts if you select internally triggered CONVERT As an output STARTSCAN reflects the actual start pulse that initiates a scan even if another PFI is externally triggering the starts You have two output options The first is an active high pulse with a pulse width of 25 to 50 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last con...

Page 63: ...ARTSCAN pulses should be separated by at least one scan period A counter on the NI 6115 6120 internally generates STARTSCAN unless you select some external source This counter is started by the TRIG1 signal and is stopped by either software or the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring ...

Page 64: ...olarity selection for either rising or falling edge The selected edge of CONVERT initiates an A D conversion As an output CONVERT reflects the actual convert pulse that is connected to the ADC even if another PFI is externally generating the conversions The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 20 and 4 21 show th...

Page 65: ...off scans in a DAQ sequence You can configure the PFI pin you select as the source for AIGATE in level detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur AIGATE can neither stop a scan in progress nor continue a previously gated off sca...

Page 66: ...0 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed This signal has a 450 ns pulse width and is software enabled Note When using NI DAQ SCANCLK polarity is low to high and cannot be changed p...

Page 67: ...iming Waveform Generation Timing Connections The AO group defined for the NI 6115 6120 is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can receive as an input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input WFTRIG is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selecti...

Page 68: ...ode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of UPDATE updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output UPDATE reflects the actual update pulse that is connected to the DACs even if another PFI is externally generating the updates The ou...

Page 69: ...can be stopped by software or the internal buffer counter BC D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can receive as an input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses UISOURCE as a clock to time the generation of the UPDA...

Page 70: ...GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTR0_SOURCE Signal Any PFI pin can receive as an input the GPCTR0_SOURCE signal which is available as an output on the PFI8 GPCTR0_SOURCE pin As an input GPCTR0_SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either ri...

Page 71: ...GPCTR0_GATE signal which is available as an output on the PFI9 GPCTR0_GATE pin As an input GPCTR0_GATE is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of applications to perform actions such as starting and stopping the counter generating...

Page 72: ... counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 32 shows the timing of GPCTR0_OUT Note When using external clocking mode with correlated DIO this pin is used as an input for the external clock Figure 4 32 GPCTR0_OUT Signal Timi...

Page 73: ... GPCTR1_SOURCE pin As an input GPCTR1_SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 even if another PFI is externally generating the source clock This output is set to high imp...

Page 74: ...ter contents As an output GPCTR1_GATE monitors the actual gate signal connected to general purpose counter 1 even if another PFI externally generates the gate This output is set to high impedance at startup Figure 4 34 shows the timing requirements for the GPCTR1_GATE signal Figure 4 34 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on...

Page 75: ...be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 36 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals Figure 4 36 GPCTR Timing Summary GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle output on TC TC tsc tsp tsp tgsu tgh tgw tout VIH VIL VIH VIL VO...

Page 76: ... edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the si...

Page 77: ...g through areas with large magnetic fields or high electromagnetic interference Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI DAQ system is the video monitor Separate the monitor from the analog signals as far as possible The following recommendations apply for all signal connections to the NI 6115 6120 Separate the NI 6115 6120 si...

Page 78: ...t and least accurate whereas the last level is the slowest most difficult and most accurate Loading Stored Calibration Constants The NI 6115 6120 is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onbo...

Page 79: ...ference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration The NI 6115 6120 has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Append...

Page 80: ...nual To externally calibrate your device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For a detailed calibration procedure for the NI 6115 6120 click Manual Calibration Procedures at ni com calibration ...

Page 81: ...ut Characteristics Number of channels 4 pseudodifferential Type of ADC Resolution NI 6115 12 bits 1 in 4 096 NI 6120 16 bits 1 in 65 536 Pipeline NI 6115 4 NI 6120 0 Sampling rate Maximum NI 6115 10 million S s NI 6120 800 kS s Minimum NI 6115 20 kS s NI 6120 No minimum Input impedance ACH to ACH Range 10 V 1 MΩ in parallel with 100 pF Range 10 V 10 kΩ in parallel with 40 pF ACH to ACHGND NI 6115 ...

Page 82: ...nges 10 V 42 V for ranges 10 V Negative input ACH 2 5 V Overvoltage protection 42 V Input current during overvoltage conditions 20 mA max Input FIFO size 16 or 32 MS Data transfers DMA interrupts programmed I O DMA modes Scatter gather DC Transfer Characteristics INL NI 6115 0 35 LSB typ 1 LSB max NI 6120 2 5 LSB max DNL NI 6115 0 25 LSB typ 1 LSB max NI 6120 0 75 LSB typ no missing codes Offset g...

Page 83: ... 2 0 12 0 5 0 058 0 060 0 35 0 69 0 061 0 0004 0 71 0 80 0 080 0 2 0 103 0 105 0 15 0 43 0 039 0 0004 0 39 0 51 0 051 Table A 2 NI 6120 Analog Input DC Accuracy Information Nominal Range V Absolute Accuracy Relative Accuracy of Reading Offset µV Noise Quantization µV Temp Drift C Absolute Accuracy at Full Scale mV Resolution µV Full Scale 24 Hours 1 Year Single Pt Averaged Single Pt Averaged 50 0 ...

Page 84: ... Table A 3 NI 6115 Analog Input Dynamic Characteristics Input Range Bandwidth MHz 1 SFDR Typ dB 2 SFDR Max dB CMRR dB 3 System Noise LSBrms 4 50 V 5 5 78 70 34 0 35 20 V 4 4 78 70 40 0 45 10 V 7 2 81 75 46 0 35 5 V 4 8 81 75 52 0 35 2 V 4 8 85 75 60 0 45 1 V 4 4 85 75 66 0 60 500 mV 4 4 85 75 70 0 80 200 mV 4 1 81 70 72 1 3 1 3 dB frequency for input amplitude at 96 of the input range 0 3 dB 2 Mea...

Page 85: ...se LSBrms 5 50 V 1 0 95 90 60 1 2 20 V 1 0 96 90 68 1 2 10 V 1 0 95 90 76 1 2 5 V 1 0 95 90 82 1 5 2 V 1 0 96 90 90 1 7 1 V 1 0 94 90 95 2 0 500 mV 1 0 90 85 100 2 2 200 mV 1 0 85 80 105 2 8 1 3 dB frequency for input amplitude at 10 of the input range 20 dB 2 Measured at 100 kHz with twelfth order bandpass filter after signal source 3 100 production tested at 100 kHz 4 DC to 60 Hz 5 LSBrms not in...

Page 86: ...ions NI 6115 6120 User Manual A 6 ni com Figure A 1 NI 6115 Total Harmonic Distortion Plus Noise THD N 0 1 38 44 50 56 62 68 74 1 0 10 0 THD N dBc Frequency MHz 10 V 5 V 2 V 1 V 0 5 V 0 2 V Full Scale 0 3 dB Input Amplitude ...

Page 87: ...nal Instruments Corporation A 7 NI 6115 6120 User Manual Figure A 2 NI 6120 Total Harmonic Distortion Plus Noise THD N Full Scale 0 3 dB Input Amplitude Frequency kHz 75 77 79 81 83 85 5 V 2 V 1 V 0 5 V 0 2 V 10 V THD N dBc 1 10 100 ...

Page 88: ...ix A Specifications NI 6115 6120 User Manual A 8 ni com Figure A 3 NI 6115 High Voltage THD N 0 1 38 44 50 56 62 68 74 1 0 10 0 THD N dBc Frequency MHz High Voltage Ranges only 10 V Input Amplitude 50 V 20 V ...

Page 89: ... Instruments Corporation A 9 NI 6115 6120 User Manual Figure A 4 NI 6120 High Voltage THD N High Voltage Ranges only 10 V Input Amplitude 80 0 80 5 81 0 81 5 82 0 82 5 83 0 83 5 84 0 84 5 85 0 1 10 100 Frequency kHz THD N dBc 50 V 20 V ...

Page 90: ...ations NI 6115 6120 User Manual A 10 ni com Figure A 5 NI 6115 THD N with Filters 10 62 63 2 65 6 66 8 68 70 4 71 6 100 1000 THD N dBc Frequency kHz With Filters Full Scale Input for Range of 1 V 69 2 64 4 50 kHz 500 kHz ...

Page 91: ...ility Recommended warm up time 15 min Offset temperature coefficient Pregain NI 6115 12 µV C NI 6120 1 5 µV C Postgain NI 6115 64 µV C NI 6120 2 1 LSB C Gain temperature coefficient NI 6115 21 3 ppm C NI 6120 22 2 ppm C With Filters Full Scale Input for Range of 1 V 75 76 77 78 79 80 81 82 83 84 85 1 10 100 Frequency kHz THD N dBc ...

Page 92: ... 6115 12 bits 1 in 4 096 NI 6120 16 bits 1 in 65 536 Max update rate 1 channel 4 MS s system dependent 2 channel 2 5 MS s system dependent Output buffer size 16 or 32 MS Data transfers DMA interrupts programmed I O DMA modes Scatter gather DC Transfer Characteristics INL NI 6115 0 5 LSB typ 2 LSB max NI 6120 0 35 LSB typ 1 LSB max DNL NI 6115 0 25 LSB typ 1 LSB max NI 6120 0 2 LSB typ 1 LSB max Of...

Page 93: ...2 V Duration 200 ms Table A 5 NI 6115 Analog Output DC Accuracy Information Nominal Range at Full Scale V Absolute Accuracy Relative Accuracy of Reading Offset mV Temp Drift C Absolute Acc at Full Scale mV Theoretical Resolution mV 24 Hrs 90 Days 1 Year 10 0 0437 0 0445 0 0454 8 9 0 0006 13 5 4 88 Table A 6 NI 6120 Analog Output DC Accuracy Information Nominal Range at Full Scale V Absolute Accura...

Page 94: ...idscale transition NI 6115 30 mV for 1 µs NI 6120 10 mV for 1 µs Settling time NI 6115 300 ns to 0 01 NI 6120 4 µs to 1 LSB Stability Offset temperature coefficient NI 6115 35 µV C NI 6120 35 µV C Gain temperature coefficient NI 6115 56 9 ppm C NI 6120 6 5 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 0 9 ppm C max Long term stabilit...

Page 95: ... word 8 bits 10 Mwords s Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Table A 7 Digital logic levels Level Min Max Input low voltage Input high voltage Input low current Vin 0 V Input high current Vin 5 V 0...

Page 96: ...og Trigger NI 6115 6120 source All analog input channels external trigger PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution NI 6115 8 bits 1 in 256 NI 6120 12 bits 1 in 4 096 Hysteresis Programmable Bandwidth 3 dB 5 MHz internal external External input PFI0 TRIG1 Impedance 10 kΩ Coupling AC DC Protection 0 5 V to VCC 0 5 V when configured ...

Page 97: ...ilable at I O connector 4 65 to 5 25 VDC at 1 A Physical Dimensions not including connectors NI PCI 6115 6120 31 2 by 10 6 cm 12 3 by 4 2 in NI PXI 6115 6120 16 by 10 cm 6 3 by 3 9 in I O connector 68 pin male SCSI II type Environmental Operating temperature 0 to 50 C Storage temperature 20 to 70 C Relative humidity 10 to 90 noncondensing 1 RTSI Trigger 6 is configured as the PXI Star Trigger for ...

Page 98: ...ry I Channel to channel 42 V Installation Category I Electromagnetic Compatibility EMC EMI CE C Tick and FCC Part 15 Class A Compliant Electrical emissions EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1998 Table 1 Note For full EMC and EMI compliance you must operate this device with shielded cabling In addition all covers and filler panels must be in...

Page 99: ...e groups AI two 24 bit two 16 bit counters AO three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 µs With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software co...

Page 100: ...et the base address for the NI 6115 6120 The base address of the NI 6115 6120 is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring the NI 6115 6120 The NI 6115 6120 is jumperless and switchless Which NI document should I read first to get started using DAQ software The DAQ Quick Start Guide and th...

Page 101: ...o 0 Figure B 1 Setting Filter Values in LabVIEW In NI DAQ use the AI_Change_Parameter function to set the filter value Set paramID to ND_Digital_Filter Set ParamValue to ND_High for a filter value of 500 kHz on the NI 6115 or 100 kHz on the NI 6120 Use ND_Low for a filter value of 50 kHz on the NI 6115 Use ND_None to disable the filter The filter is disabled by default I have connected a different...

Page 102: ...sition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows If you are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW If you are using LabVIEW select Data Acquisition Calibration and Configuration Route Signal vi from the function palette a...

Page 103: ...nction Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines ...

Page 104: ...se lines may have pull up or pull down resistors connected to them as shown in Table 4 5 Digital I O Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 is in the high impedance state after power on and Table 4 5 shows that there is a 50 kΩ pull up resistor This pull up resistor sets the DIO 0 pin to a logic high when the output is in a...

Page 105: ...d Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email Training Visit ni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world Sy...

Page 106: ...ng Value p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 Numbers Symbols degree greater than greater than or equal to less than less than or equal to per percent plus or minus positive of or plus negative of or minus Ω ohm square root of 5 V 5 VDC source signal ...

Page 107: ... that causes signals with frequencies higher than half the sampling frequency to appear as lower frequency components in a frequency spectrum ANSI American National Standards Institute AO analog output AOGND analog output ground signal ASIC application specific integrated circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions B Bessel filter ...

Page 108: ...r timer a circuit that counts external pulses or clock pulses timing CTR counter D D A digital to analog DAC digital to analog converter an electronic device that converts a digital number into a corresponding analog voltage or current DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DAQ data acquisition 1 collecting and measuring electrical signals from sensors transd...

Page 109: ...r ground whose difference is measured DIO digital input output DIP dual inline package dithering the addition of Gaussian noise to an analog input signal for the purpose of increasing the resolution of a measurement when using averaging DMA direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something...

Page 110: ...signals that are not connected to an absolute reference or system ground also called nonreferenced signal sources FPGA field programmable gate array FREQ_OUT frequency output signal G gain the factor by which a signal is amplified sometimes expressed in decibels GATE gate signal GPCTR general purpose counter signal GPCTR0_GATE general purpose counter 0 gate signal GPCTR0_OUT general purpose counte...

Page 111: ...cans read or updates written per second I I O input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces impedance resistance in inch or inches INL integral nonlinearity a measurement in least significant bits of the worst case deviation from the ideal A D or D A transfer characteristic of ...

Page 112: ...er a read or a write MAX Measurement and Automation Explorer MB megabytes of memory Measurement Studio a set of test and measurement oriented software tools from National Instruments for C C and Visual Basic users MHz megahertz MIO multifunction I O MITE MXI Interface to Everything MSB most significant bit mux multiplexer a switching device with multiple inputs that sequentially connects each of i...

Page 113: ...or thermocouples with voltage signals that are not connected to an absolute reference or system ground also called nonreferenced signal sources Nyquist frequency the maximum signal frequency that a sampling system can accurately represent in frequency spectrum measurement which is half the sampling frequency O OUT output pin a counter output pin where the counter can generate various TTL pulse wav...

Page 114: ...eudodifferential channels are all referred to a common ground but this ground is not directly connected to the computer ground Often this connection is made by a relatively low value resistor to give some isolation between the two grounds pu pull up PWB printed wire board PXI PCI eXtensions for Instrumentation an open specification that builds off the CompactPCI specification by adding instrumenta...

Page 115: ...ization of functions RTSI_OSC RTSI Oscillator RTSI bus master clock S s seconds S samples S s samples per second used to express the rate at which a DAQ device samples an analog signal SCANCLK scan clock signal scatter gather a term that describes very high speed DMA burst mode transfers that are made only by the bus master signal conditioning the manipulation of signals to prepare them for digiti...

Page 116: ... a percentage thermocouple a temperature sensor created by joining two dissimilar metals whose junction produces a small voltage as a function of the temperature toff an offset delayed pulse the offset is t nanoseconds from the falling edge of the CONVERT signal tout output delay time tp period of a pulse train TRIG trigger signal tsc source clock period tsp source pulse width TTL transistor trans...

Page 117: ...a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program Vin volts in Vm measured voltage VOH volts output high VOL volts output low VOUT volts out Vrms volts root mean square Vs ground referenced signal source W...

Page 118: ...renced signal sources 4 9 nonreferenced signal sources 4 11 pseudodifferential connections definition 4 8 ground referenced signals figure 4 9 analog input specifications DC transfer characteristics A 2 dynamic characteristics A 4 input characteristics A 1 stability A 11 analog output overview 3 5 questions about B 3 signal connections 4 14 analog output specifications DC transfer characteristics ...

Page 119: ...igure 3 13 RTSI triggers 3 12 timing signal routing 3 10 using PXI with CompactPCI 1 2 C cables See also I O connectors custom cabling 1 6 field wiring considerations 4 39 optional equipment 1 6 calibration external calibration 5 2 loading calibration constants 5 1 self calibration 5 2 clocks correlating DIO signals 4 16 device and RTSI clocks 3 12 commonly asked questions See questions and answer...

Page 120: ...ng questions about B 4 device clocks 3 12 device configuration See configuration DGND signal description table 4 3 digital I O signal connections 4 15 power connections 4 18 diagnostic resources C 1 digital I O See also DGND signal See also DIO 0 7 signal correlated clock signal driving DI and DO signals figure 4 17 description 3 10 falling edge RTSI clock signal driving DIO signal figure 4 18 ris...

Page 121: ...r timing summary figure 4 37 general purpose timing connections 4 33 RTSI bus signal connections figure 3 13 GPCTR0_OUT signal description table 4 5 general purpose counter timing summary figure 4 37 general purpose timing connections 4 34 RTSI bus signal connections figure 3 13 signal summary table 4 7 GPCTR0_SOURCE signal See also PFI8 GPCTR0_SOURCE signal general purpose counter timing summary ...

Page 122: ...clocks 3 12 overview 3 10 programmable function inputs 3 12 RTSI triggers 3 12 STARTSCAN signal routing figure 3 11 help professional services C 1 technical support C 1 high hysteresis analog triggering mode 3 7 highValue 3 5 I I O connectors exceeding maximum ratings caution 4 1 overview 4 1 pin assignments figure 4 2 signal descriptions table 4 3 input coupling 3 4 input polarity and range bipol...

Page 123: ...technical support C 1 optional equipment 1 6 P PFI0 TRIG1 signal See also TRIG1 signal analog triggering 3 5 description table 4 4 signal summary table 4 6 PFI1 TRIG2 signal See also TRIG2 signal description table 4 4 signal summary table 4 6 PFI2 CONVERT signal See also CONVERT signal description table 4 4 signal summary table 4 6 PFI3 GPCTR1_SOURCE signal See also GPCTR1_SOURCE signal descriptio...

Page 124: ... 6 pretriggered data acquisition 4 21 professional services C 1 programmable function inputs PFIs See PFIs programmable function inputs programming examples C 1 pseudodifferential signal connections definition 4 8 ground referenced signals figure 4 9 PXI PXI 6115 6120 J2 pin assignments table 1 3 using with CompactPCI 1 2 Q questions and answers analog input and output B 3 general information B 1 ...

Page 125: ...gnal 4 36 GPCTR1_OUT signal 4 36 GPCTR1_SOURCE signal 4 35 GPCTR1_UP_DOWN signal 4 37 I O connectors exceeding maximum ratings caution 4 1 overview 4 1 signal descriptions table 4 3 power connections 4 18 programmable function input connections 4 20 timing connections data acquisition timing connections 4 20 general purpose timing signal connections 4 32 waveform generation timing connections 4 29...

Page 126: ...timebase clocks 3 12 timing connections data acquisition timing connections AIGATE signal 4 27 CONVERT signal 4 26 EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 27 STARTSCAN signal 4 24 TRIG1 signal 4 21 TRIG2 signal 4 22 typical posttriggered acquisition figure 4 21 typical pretriggered acquisition figure 4 21 general purpose timing signal connections FREQ_OUT signal 4 38 GPCTR0_GAT...

Page 127: ... 31 RTSI bus signal connections figure 3 13 unpacking NI 6115 6120 1 7 UPDATE signal See also PFI5 UPDATE signal input timing figure 4 31 output timing figure 4 31 RTSI bus signal connections figure 3 13 timing connections 4 30 using with UISOURCE signal 4 31 using with WFTRIG signal 4 29 V VCC signal table 4 6 voltage output specifications A 13 working voltage range 4 13 voltage controlled crysta...

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