Chapter 4
Connecting Signals
©
National Instruments Corporation
4-31
Figures 4-27 and 4-28 show the timing requirements for UPDATE*.
Figure 4-27.
UPDATE* Input Signal Timing
Figure 4-28.
UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the DAC
latches.
The UI counter for the NI 6115/6120 normally generates UPDATE* unless
you select some external source. The UI counter is started by the WFTRIG
signal and can be stopped by software or the internal buffer counter (BC).
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.
UISOURCE Signal
Any PFI pin can receive as an input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses
UISOURCE as a clock to time the generation of the UPDATE* signal. You
must configure the PFI pin you select as the source for UISOURCE in the
level-detection mode. You can configure the polarity selection for the PFI
pin for either active high or active low. Figure 4-29 shows the timing
requirements for UISOURCE.
Rising-Edge
Polarity
Falling-Edge
Polarity
t
w
= 10 ns minimum
t
w
t
w
t
w
= 50 – 75 ns
