NI 5772 CLIP
The NI 5772 ships with the following CLIP items:
•
NI 5772 CLIP
—This CLIP provides access to two analog input channels, eight
bidirectional DIO channels, four bidirectional PFI channels, and an input clock selector
that can be configured to use one of the following settings:
–
Internal Sample Clock
–
Internal Sample Clock locked to an external Reference Clock through the REF IN
connector
–
External Sample Clock through the CLK IN connector
–
Internal Sample Clock locked to an external Reference Clock through
IoModSyncClock
The CLIP also contains an engine to program the ADC and Sample Clock circuit, either
through predetermined settings for an easier instrument setup, or through a raw SPI
address and data signals for a more advanced setup. In the LabVIEW FPGA Module,
12-bit analog input data is accessed using an I16 data type (left-justified). The DIO
signals are grouped into two ports of four signals each and are accessed using a U8 data
type and a Boolean write enable signal. The four PFI signals are accessed individually
using Boolean indicators.
Although real-time sampling is the default sampling mode on the NI 5772, the NI 5772
CLIP also supports Time-Interleaved Sampling (TIS) on one analog input channel at a
time. TIS enables the device to use both channels on the ADC to sample the same input
channel at different relative phases, which doubles the real-time sampling rate. The
NI 5772 then interleaves the samples to create a waveform as if only one ADC channel
was sampling the waveform at twice the Sample Clock rate. The data is returned on the
AI 0 Data <
N
..
N
-3> and AI 1 Data <
N
..
N
-3> signals even though the device is only
sampling the single analog input channel that you selected. To configure the NI 5772 for
TIS mode using this CLIP, refer to the
NI FlexRIO Adapter Module Support
book in the
NI FlexRIO Help
.
The following figure demonstrates TIS on an NI 5772 device.
10 |
NI 5772R User Manual and Specifications
| ni.com
Summary of Contents for NI 5772R
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