Figure 1. NI 5751 Hardware Block Diagram
I16
I16
I16
AI A0
AI A7
Analog
Connector
ADC
B
ADC
A
Deserializer
I16
AI B8
AI B15
Deserializer
AI 0
AI 7
AI 8
AI 15
DI 0
DI 7
DO 0
Sync Clock
(DStarA)
DO 7
External Clock In
Clock
Multiplexer
50 MHz Internal
Oscillator
Digital
Connector
Sample Clock Select
SPI Write
SPI Device Select
SPI Address
SPI Write Data
Force Initialization
Initialization Done
PLL Unlocked
ADC Error A
ADC Error B
SPI
Engine
NI 5751 Adapter Module
LabVIEW FPGA CLIP
Data Clock
ADC
Control
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for
HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and
socketed.
■
User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling
VHDL code to communicate directly with an FPGA VI.
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NI-5751/5751B
Summary of Contents for NI 5751
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