Chapter 8
Programmable Function Interfaces (PFI)
©
National Instruments Corporation
8-7
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 8-1.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 8-5 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
Figure 8-5.
Filter Example
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425
μ
s filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025
μ
s.
When a PFI input is routed directly to RTSI, or a RTSI input is routed
directly to PFI, the s Series device does not use the filtered version of the
input signal.
Refer to the KnowledgeBase document,
Digital Filtering with M Series
and CompactDAQ
, for more information about digital filters and counters.
To access this KnowledgeBase, go to
ni.com/info
and enter the info
code
rddfms
.
Table 8-1.
Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns
5
125 ns
100 ns
6.425
μ
s
257
6.425
μ
s
6.400
μ
s
2.56 ms
~101,800
2.56 ms
2.54 ms
Disabled
—
—
—
1 2
3
1 4
1
2
3
4 5
RT
S
I, PFI, or
PXI_
S
TAR Termin
a
l
Filter Clock
(40 MHz)
Filtered Inp
u
t
Filtered inp
u
t goe
s
high when termin
a
l
i
s
sa
mpled high on
five con
s
ec
u
tive filter
clock
s
.
