Chapter 1
Getting Started
©
National Instruments Corporation
1-13
A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF
OUT connector on the rear of the chassis. Refer to Figure 1-2 for the
location of this connector. This clock is driven by an independent buffer.
Refer to Appendix A,
, for the specification information for
the 10 MHz REF OUT signal on the rear panel of the chassis.
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/
n
MHz, where
n
is a positive
integer. The default for
n
is 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows
n
to be programmed to other integers. For
instance, setting
n
= 3 gives a PXIe_SYNC100 with a 300ns period while
still maintaining its phase relationship to PXI_CLK10. The value for
n
may
be set to any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL for use when
n
> 1. Refer to Table B-6,
Connector Pinout for the System Timing Slot
, for system timing slot pinout.
Refer to Appendix A,
, for the PXIe_SYNC_CTRL input
specifications.
By default, a high-level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge the
PXIe_SYNC100 signal will restart. This will allow several chassis to have
their PXIe_SYNC100 in phase with each other. Refer to Figure 1-8 for
timing details with this method.
Figure 1-8.
PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
PXI_CLK10
PXIe_
S
YNC_CTRL
PXIe_
S
YNC100
S
YNC100 Divider
Re
s
t
a
rted Here
