Glossary
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National Instruments Corporation
G-3
PCI-Based MXI-2 Interface for Windows
bus error
An error that signals failed access to an address. Bus errors occur with
low-level accesses to memory and usually involve hardware with bus
mapping capabilities. For example, nonexistent memory, a nonexistent
register, or an incorrect device access can cause a bus error.
bus master
A device that is capable of requesting the Data Transfer Bus (DTB) for the
purpose of accessing a slave device
byte order
How bytes are arranged within a word or how words are arranged within a
longword. Motorola ordering stores the most significant (MSB) byte or
word first, followed by the least significant byte (LSB) or word. Intel
ordering stores the LSB or word first, followed by the MSB or word.
C
CLK10
A 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
Commander
A message-based device that is also a bus master and can control one or
more Servants
CompactPCI
An adaptation of the PCI specification for industrial and/or embedded
applications that require a more robust mechanical form factor than desktop
PCI. CompactPCI provides a standard form factor for those applications
requiring the high performance of PCI as well as the small size and
ruggedness of a rack-mount system.
configuration
registers
A set of registers through which the system can identify a module device
type, model, manufacturer, address space, and memory requirements.
To support automatic system and memory configuration, the VXIbus
specification requires that all VXIbus devices have a set of such registers.
D
daisy-chain
A method of propagating signals along a bus, in which the devices are
prioritized on the basis of their position on the bus
Data Transfer Bus
DTB; one of four buses on the VMEbus backplane. The DTB is used by
a bus master to transfer binary data between itself and a slave device.
