V
CC1
V
CC1
V
EE2
V
CC1
EVM Setup and Precautions
2.2
Signal Connections
illustrates the ISO5851 EVM signal path schematic.
Figure 3. ISO5851 EVM Signal Path Schematic
2.2.1
I/O Connections
shows the signal path schematic of the EVM. JMP1 allows for stimulus or monitoring of the
device I/O pins IN+, IN-, RDY, FLT, and RST. Test points 1, 2, 3, 4, and 5 provide additional access to the
I/O pins. The EVM comes populated with 10-k
Ω
pullup resistors (R1, R2) on the RDY and FLT pins, as
well as 220-pF capacitors (C4, C5) to GND1 for noise filtering.
2.2.2
Output and Loading
The EVM comes populated with a 1-nF load (C12) on the output side. The output can be monitored
directly via TP12. A 10:1 resistor-divider network is provided for monitoring the output with a low-voltage
probe via TP20. The divider circuit can be disconnected from the output by removing the shunt on JMP5.
10-
Ω
gate resistors (R3, R12) control the rise and fall times of the output. These resistors can be modified
by the user to alter the turn-on and turn-off characteristics of the output.
The EVM also allows for evaluation of the device with an IGBT load in either of the standard TO-247 or
TO-220 footprints. During evaluation with an IGBT load, the pre-installed capacitive load (C12) can be
disconnected from the output by removing the shunt on JMP2.
The EVM provides an additional connection (P2) for applying an external power supply to the IGBT
Collector. The EVM is not intended for high voltage testing and the voltage applied to P2 should be limited
to 50-V DC.
When evaluating the device with an IGBT load using P2, the components D1, D2, R7, and C13 should be
populated with their default values, specified in
. Additionally, ensure that the DESAT pin is
not
connected to GND2 when driving an IGBT load using P2, either by removing R8, or verifying that all
jumpers are removed from JMP3.
4
ISO5851 Evaluation Module
SLLU218 – June 2015
Copyright © 2015, Texas Instruments Incorporated
