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PCI-6023E/6024E/6025E Hardware and Software
Configuration Form

Record the settings and revisions of your hardware and software on the line to the right of each item.
Complete a new copy of this form each time you revise your software or hardware configuration, and
use this form as a reference for your current configuration. Completing this form accurately before
contacting National Instruments for technical support helps our applications engineers answer your
questions more efficiently.

National Instruments Products

Hardware revision _______________________________________________________________

Interrupt level of hardware _________________________________________________________

DMA channels of hardware ________________________________________________________

Base I/O address of hardware _______________________________________________________

Programming choice _____________________________________________________________

National Instruments software ______________________________________________________

Other boards in system ____________________________________________________________

Base I/O address of other boards ____________________________________________________

DMA channels of other boards _____________________________________________________

Interrupt level of other boards ______________________________________________________

Other Products

Computer make and model ________________________________________________________

Microprocessor __________________________________________________________________

Clock frequency or speed __________________________________________________________

Type of video board installed _______________________________________________________

Operating system version __________________________________________________________

Operating system mode ___________________________________________________________

Programming language ___________________________________________________________

Programming language version _____________________________________________________

Other boards in system ____________________________________________________________

Base I/O address of other boards ____________________________________________________

DMA channels of other boards _____________________________________________________

Interrupt level of other boards ______________________________________________________

PCI.book Page 5 Wednesday, September 16, 1998 9:09 AM

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Summary of Contents for DAQ PCI-6023E

Page 1: ...6023E 6024E 6025E User Manual Multifunction I O Boards for PCI Bus Computers PCI 6023E 6024E 6025E User Manual October 1998 Edition Part Number 322072A 01 PCI book Page 1 Wednesday September 16 1998...

Page 2: ...5 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 0...

Page 3: ...DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence...

Page 4: ...ogramming Choices 1 3 National Instruments Application Software 1 3 NI DAQ Driver Software 1 3 Register Level Programming 1 5 Optional Equipment 1 6 Chapter 2 Installation and Configuration Software I...

Page 5: ...tions for Floating Signal Sources RSE Configuration 4 18 Single Ended Connections for Grounded Signal Sources NRSE Configuration 4 18 Common Mode Signal Rejection Considerations 4 19 Analog Output Sig...

Page 6: ...PCTR0_OUT Signal 4 45 GPCTR0_UP_DOWN Signal 4 45 GPCTR1_SOURCE Signal 4 46 GPCTR1_GATE Signal 4 46 GPCTR1_OUT Signal 4 47 GPCTR1_UP_DOWN Signal 4 47 FREQ_OUT Signal 4 49 Field Wiring Considerations 4...

Page 7: ...Input Connections for Ground Referenced Signals 4 19 Figure 4 9 Analog Output Connections 4 20 Figure 4 10 Digital I O Connections 4 21 Figure 4 11 Digital I O Connections Block Diagram 4 22 Figure 4...

Page 8: ...PCTR1_SOURCE Signal Timing 4 46 Figure 4 39 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 47 Figure 4 40 GPCTR1_OUT Signal Timing 4 47 Figure 4 41 GPCTR Timing Summary 4 48 Figure B 1 68 Pin E Se...

Page 9: ...and configure your board Chapter 3 Hardware Overview presents an overview of the hardware functions on your board Chapter 4 Signal Connections describes how to make input and output signal connection...

Page 10: ...y data loss or a system crash bold Bold text denotes the names of menus menu items parameters dialog boxes dialog box buttons or options icons windows Windows 95 tabs or LEDs bold italic Bold italic t...

Page 11: ...nual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions Your DAQ hardware documentation This documentation has detailed information about t...

Page 12: ...ou should not need the register level programmer manual if you are using National Instruments driver or application software Using NI DAQ ComponentWorks LabVIEW LabWindows CVI Measure or VirtualBench...

Page 13: ...of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing r...

Page 14: ...installing your board Unpacking Your board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid...

Page 15: ...LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming...

Page 16: ...d performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ de...

Page 17: ...oftware can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program your N...

Page 18: ...Real Time System Integration bus cables SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up...

Page 19: ...n software refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package If you are a register level programmer refer to the PCI...

Page 20: ...r devices The following are general installation instructions Consult your computer user manual or technical reference manual for specific instructions and warnings 1 Write down your board s serial nu...

Page 21: ...Analog Mode Multiplexer Analog Input Muxes Voltage REF Calibration DACs Dither Generator Calibration DACs 82C55A DAC0 DAC1 NOT ON 6023E Analog Output DAQ STC Analog Input Timing Control Analog Output...

Page 22: ...three configurations refer to the Analog Input Signal Overview section in Chapter 4 Signal Connections Input Range The PCI 6023E PCI 6024E and PCI 6025E boards have a bipolar input range that changes...

Page 23: ...ving averaging or spectral analysis you may want to disable the dither to reduce noise Your software enables and disables the dither circuitry Figure 3 2 illustrates the effect of dither on signal acq...

Page 24: ...a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the a Dith...

Page 25: ...s reason keep source impedances under 1 k to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not...

Page 26: ...idirectional I O mode 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits plus control and status bits from Port C PC Modes 1 and 2 use ha...

Page 27: ...ailable on the board connector as PFI 0 9 and are connected to the board s internal signal routing multiplexer for each timing signal Software can select any one of the PFI pins as the external source...

Page 28: ...lso program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used...

Page 29: ...ctions section of Chapter 4 Signal Connections for a description of the signals shown in Figure 3 4 RTSI Bus Connector switch RTSI Switch Clock Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCT...

Page 30: ...pin accessories with the SH1006868 shielded cable or to 50 pin accessories with the R1005050 ribbon cable I O Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the PCI 60...

Page 31: ...4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND 1 Not available on the PCI 6023E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK...

Page 32: ...51 FREQ_OUT GND GPCTR0_OUT 5 V PFI9 GPCTR0_GATE GND PFI8 GPCTR0_SOURCE PA0 PFI7 STARTSCAN GND PFI6 WFTRIG PA1 PFI5 UPDATE GND GPCTR1_OUT PA2 PFI4 GPCTR1_GATE GND PFI3 GPCTR1_SOURCE PA3 PFI2 CONVERT G...

Page 33: ...tput of analog output channel 1 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND andDGND areconnected together on your PCI E Se...

Page 34: ...ut PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 AI Stop Trigger signal In pretrigger applications a low to high transition indicates the initiation of the posttrig...

Page 35: ...log input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source As an input this is one of the PFIs As an output...

Page 36: ...V s DAC1OUT 6024E and 6025E only AO 0 1 Short circuit to ground 5 at 10 5 at 10 8 V s AOGND AO DGND DO VCC DO 0 1 Short circuit to ground 1A fused DIO 0 7 DIO V cc 0 5 13 at V cc 0 4 24 at 0 4 1 1 50...

Page 37: ...V cc 0 4 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at V cc 0 4 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO V cc 0 5 3 5 at V cc 0 4 5 at 0 4 1 5...

Page 38: ...is therefore already connected to a common ground point with respect to the board assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that...

Page 39: ...are listed in the Protection column of Table 4 2 In NRSE mode the AISENSE signal is connected internally to the negative input of the PGIA when their corresponding channels are selected In DIFF and R...

Page 40: ...e RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section in this chapter If you have a grounded source...

Page 41: ...rounded Signal Source Examples Ungrounded Thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in instruments with nonisolated outputs V1 ACH V1 ACH ACH See text for i...

Page 42: ...ltiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available You should use differ...

Page 43: ...ns for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the board grou...

Page 44: ...signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA The PGIA will then saturate causing e...

Page 45: ...n the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 6 This full...

Page 46: ...re recommended for greater signal integrity for any input signal that does not meet the preceding conditions Using your software you can configure the channels for two different types of single ended...

Page 47: ...ries PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference...

Page 48: ...PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup...

Page 49: ...e voltage output signal for analog output channel 0 DAC1OUT is the voltage output signal for analog output channel 1 AOGND is the ground reference signal for both analog output channels and the extern...

Page 50: ...an program all lines individually to be inputs or outputs Figure 4 10 shows signal connections for three typical digital I O applications Figure 4 10 Digital I O Connections Figure 4 10 shows DIO 0 3...

Page 51: ...y The PCI 6025E board uses an 82C55A PPI to provide an additional 24 lines of digital I O that represent three 8 bit ports PA PB and PC Each port can be programmed as an input or output port Figure 4...

Page 52: ...for each configuration You can also use ports A and B in different modes the table does not show every possible combination Note Table 4 3 shows both the port C signal assignments and the terminology...

Page 53: ...imum of 0 4 VDC The DIO lines provide a maximum of 2 5 mA at 3 7 V in the high state Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull dow...

Page 54: ...other circuitry connected to this line The 7 1 k resistor reduces the amount of logic high source current by 0 4 mA with a 2 8 V output Timing Specifications PCI 6025E Only This section lists the timi...

Page 55: ...when the 82C55A requests service during a data transfer The appropriate interrupt enable bits must be set to generate this signal RD Internal Read This signal is the read signal generated from the co...

Page 56: ...ows Figure 4 13 Timing Specifications for Mode 1 Input Transfer Name Description Minimum Maximum T1 STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data aft...

Page 57: ...1 are as follows Figure 4 14 Timing Specifications for Mode 1 Output Transfer Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T...

Page 58: ...2 Bidirectional Transfer Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK...

Page 59: ...external control over the timing of your board is routed through the 10 programmable function inputs labeled PFI 0 9 These signals are explained in detail in the section Programmable Function Input Co...

Page 60: ...applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I...

Page 61: ...the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIG...

Page 62: ...h and is software enabled Figure 4 19 shows the timing for the SCANCLK signal Figure 4 19 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse...

Page 63: ...ising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions As an output the TRIG1 signal reflects the action...

Page 64: ...the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2...

Page 65: ...or STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internal...

Page 66: ...lses are masked off until the board generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If...

Page 67: ...ed in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initia...

Page 68: ...hich is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either th...

Page 69: ...some external source Figure 4 29 shows the timing requirements for the SISOURCE signal Figure 4 29 SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your boar...

Page 70: ...nput the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected...

Page 71: ...or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can e...

Page 72: ...R1_UP_DOWN and FREQ_OUT GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal which is available as an output on the PFI8 GPCTR0_SOURCE pin As an input the GPCTR0_SOURCE signa...

Page 73: ...As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling...

Page 74: ...electable for both options This output is set to tri state at startup Figure 4 37 shows the timing of the GPCTR0_OUT signal Figure 4 37 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can b...

Page 75: ...GPCTR1_SOURCE signal Figure 4 38 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MH...

Page 76: ...1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Fi...

Page 77: ...or to one of the internally generated signals on your board Figure 4 41 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10...

Page 78: ...nsiderations Environmental noise can seriously affect the accuracy of measurements made with your board if you do not take proper care when running signal wires between signal sources and the board Th...

Page 79: ...uce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also...

Page 80: ...bration Constants Your board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were...

Page 81: ...ments you can ignore a small amount of gain error and self calibration should be sufficient External Calibration Your board has an onboard calibration reference to ensure the accuracy of self calibrat...

Page 82: ...calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this c...

Page 83: ...acteristics Number of channels 16 single ended or 8 differential software selectable per channel Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Sampling rate 200 kS s guaranteed In...

Page 84: ...ive FS 24 Hours 90 Days 1 Year mV Single Pt Averaged C Theoretical Averaged 10 10 0 0722 0 0742 0 0764 6 385 3 906 0 975 0 0010 4 883 1 284 5 5 0 0272 0 0292 0 0314 3 203 1 953 0 488 0 0005 2 441 0 64...

Page 85: ...r after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 75 of reading...

Page 86: ...tability Recommended warm up time 15 min Offset temperature coefficient Pregain 15 V C Postgain 240 V C Gain temperature coefficient 20 ppm C Analog Output PCI 6024E and PCI 6025E only Output Characte...

Page 87: ...5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 m...

Page 88: ...amic Characteristics Settling time for full scale step 10 s to 0 5 LSB accuracy Slew rate 10 V s Noise 200 Vrms DC to 1 MHz Glitch energy at midscal transition Magnitude 12 mV Duration 2 0 s Stability...

Page 89: ...100 k pull up to 5VDC Level Min Max Input low voltage Input high voltage Input low current Vin 0 V Input high current Vin 5 V 0 V 2 V 0 8 V 5 V 320 A 10 A Output low voltage IOL 24 mA Output high vol...

Page 90: ...4 bits Frequency scalers 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scalers 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min sou...

Page 91: ...ppm Power Requirement 5 VDC 5 0 7 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 17 5 by 10 6 cm 6 9 by 4 2 in I O connector PCI 6023E 602...

Page 92: ...rential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately from the digital lines When using a cable shield use separate shie...

Page 93: ...ber 749081 1 AMP backshell 0 55 max O D cable part number 749854 1 Optional Connectors Figure B 1 shows the pin assignments for the 68 pin E Series connector This connector is available when you use t...

Page 94: ...ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND 1 Not available on the PCI 6023E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANC...

Page 95: ...put Connector Pin Assignments N C N C N C N C N C N C N C N C N C 5 V PA0 GND PA2 PA3 GND PA5 PA6 GND PB0 PB1 GND GND PB4 PB5 GND PB7 PC0 GND PC2 PC3 GND PC5 PC6 GND N C N C N C N C N C N C N C N C N...

Page 96: ...Connector Pin Assignments GPCTR0_OUT PFI8 GPCTR0_SOURCE PFI6 WFTRIG GPCTR1_OUT PFI3 GPCTR1_SOURCE PFI1 TRIG2 EXTSTROBE 5 V DGND DIO3 DIO2 DIO1 DIO0 AOGND DAC1OUT1 AISENSE ACH7 ACH6 ACH5 ACH4 ACH3 ACH2...

Page 97: ...sembly with the PCI 6025E Figure B 4 50 Pin Extended Digital Input Connector Pin Assignments 5 V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND...

Page 98: ...unters The groups can be configured independently with timing resolutions of 50 ns or 10 s With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The...

Page 99: ...d drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are i...

Page 100: ...nal for A D conversion comes from PFI5 as follows If you are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW If you are using LabVIEW invoke AI Clock Config VI with...

Page 101: ...ure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the...

Page 102: ...le 4 2 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 2 shows that there is a 50 k pu...

Page 103: ...uestions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS an...

Page 104: ...ry contact the source from which you purchased your software to obtain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 0...

Page 105: ...____________________________________________________________ _______________________________________________________________________________ National Instruments hardware product model _____________ R...

Page 106: ...dress of other boards ____________________________________________________ DMA channels of other boards _____________________________________________________ Interrupt level of other boards __________...

Page 107: ...____________________________________________________________________ _______________________________________________________________________________ ___________________________________________________...

Page 108: ...6 m milli 10 3 k kilo 103 M mega 106 G giga 109 t tera 1012 Numbers Symbols percent positive of or plus negative of or minus per degree ohm A A amperes AC alternating current AC coupled allowing the...

Page 109: ...of signal conditioning that improves accuracy in the resulting digitized signal and reduces noise ANSI American National Standards Institute AO analog output AOGND analog output ground signal ASIC App...

Page 110: ...ors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the ISA and PCI bus bus master a...

Page 111: ...le of sourcing or sinking while still operating within voltage range specifications current sinking the ability of a DAQ board to dissipate current for analog or digital output signals current sourcin...

Page 112: ...ss a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to fro...

Page 113: ...update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device filterin...

Page 114: ...ter Also called IEEE 488 bus because it is defined by ANSI IEEE Standards 488 1978 488 1 1987 and 488 2 1987 grounded measurement system See referenced single ended measurement system H h hour half po...

Page 115: ...proportional to the difference between the voltages at its two high impedance inputs interrupt a computer signal indicating that the CPU should suspend its current task to service a designated activi...

Page 116: ...t are not linked linearity the adherence of device response to the equation R KS where R response S stimulus and K a constant LSB least significant bit M MIO multifunction I O MITE MXI Interface to Ev...

Page 117: ...d signal sources are batteries transformers or thermocouples NRSE nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage a...

Page 118: ...ices devices that do not require DIP switches or jumpers to configure resources on the devices also called switchless devices port 1 a communications connection on a computer or a remote controller 2...

Page 119: ...LSB of the accuracy of an ADC It includes all non linearity and quantization errors It does not include offset and gain errors of the circuitry feeding the ADC resolution the smallest signal incremen...

Page 120: ...an clock the clock controlling the time interval between scans scan rate the number of scans per second For example a scan rate of 10 Hz means sampling each channel 10 times per second SCXI Signal Con...

Page 121: ...sition software triggering a method of triggering in which you simulate an analog trigger using software Also called conditional retrieval SOURCE source signal SS simultaneous sampling a property of a...

Page 122: ...rate measured in bytes s at which data is moved from source to destination after software initialization and set up operations the maximum rate at which the hardware can operate TRIG trigger signal t...

Page 123: ...interface and a block diagram program VIH volts input high VIL volts input low Vin volts in Vm measured voltage VOH volts output high VOL volts output low Vref reference voltage Vrms volts root mean...

Page 124: ...des 4 8 to 4 19 available input configurations table 3 2 common mode signal rejection considerations 4 19 differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreferenced or f...

Page 125: ...to B 2 customer communication xiv D 1 to D 2 D DAC0OUT signal analog output signal connections 4 20 description table 4 4 signal summary table 4 7 DAC1OUT signal analog output signal connections 4 20...

Page 126: ...on table 4 5 signal summary table 4 7 F fax and telephone support numbers D 2 Fax on Demand support D 2 field wiring considerations 4 49 to 4 50 floating signal sources description 4 9 differential co...

Page 127: ...e B 5 50 pin extended digital input connector pin assignments figure B 6 68 pin E Series connector pin assignments figure B 3 68 pin extended digital input connector pin assignments figure B 4 pin ass...

Page 128: ...hardware overview block diagram 3 1 features 1 1 optional equipment 1 6 requirements for getting started 1 2 software programming choices 1 3 to 1 5 ComponentWorks 1 3 LabVIEW and LabWindows CVI 1 3 N...

Page 129: ...umentation amplifier Q questions and answers C 1 to C 5 analog input and output C 2 to C 3 general information C 1 installation and configuration C 2 timing and digital I O C 3 to C 5 R RD signal desc...

Page 130: ...ration timing connections 4 40 to 4 43 timing specifications 4 25 to 4 29 mode 1 input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 signal names used in...

Page 131: ...T signal 4 49 GPCTR0_GATE signal 4 44 to 4 45 GPCTR0_OUT signal 4 45 GPCTR0_SOURCE signal 4 43 to 4 44 GPCTR0_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal 4 47 GPCTR1_UP_DOWN...

Page 132: ...veform generation questions about C 2 to C 3 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG signal 4 40 to 4 41 WFTRIG signal 4 40 t...

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