Chapter 3 Hardware Overview
©
National Instruments Corporation 3-15 PCI-4451/4452/4453/4454 User Manual
♦
PCI-4451/4452/4453/4454
The DDS clock signal and the synchronization start signal are transmitted
to other PCI-bus DSA devices through the RTSI bus. The PCI-445X can
also receive these signals to synchronize the acquisition or waveform
generation with other devices. In a multidevice system, a master device
drives the clock and synchronization signal to other slave or receiving
devices.
Device Configuration Issues
Selecting a sample rate that is less than two times the frequency of a band
of interest can lead you to believe the device is functioning improperly.
By undersampling the signal, you might receive what appears to be a DC
signal. This situation is due to the sharp antialiasing filters that remove
frequency components above the sampling frequency. If you have a
situation where this occurs, simply increase the sample rate until it meets
the requirements of the Nyquist Sampling Theorem. For more information
on the filters and aliasing, refer to Chapter 6,
Unlike other converter technologies, delta-sigma converters must be run
continuously and at a minimum clock rate. To operate within guaranteed
specifications, the A/D converters must operate at a minimum sample rate
of 5.0 kS/s and the D/A converters must operate at a minimum update rate
of 1.25 kS/s. This minimum rate is required to keep the internal circuitry of
the converters running within specifications. You are responsible for
selecting sample and update rates that fall within the specified limits.
Failure to do so can greatly affect the specifications.
