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Chapter 4 Signal Connections

AT-MIO/AI E Series User Manual

4-40



National Instruments Corporation

Figures 4-23 and 4-24 show the input and output timing requirements
for the CONVERT* signal.

Figure 4-23.

CONVERT* Input Signal Timing

Figure 4-24.

CONVERT* Output Signal Timing

The ADC switches to hold mode within 60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary
from one conversion to the next. Separate the CONVERT* pulses by at
least one conversion period.

The sample interval counter on the AT E Series board normally
generates the CONVERT* signal unless you select some external
source. The counter is started by the STARTSCAN signal and
continues to count down and reload itself until the scan is finished. It
then reloads itself in readiness for the next STARTSCAN pulse.

A/D conversions generated by either an internal or external
CONVERT* signal are inhibited unless they occur within a data
acquisition sequence. Scans occurring within a data acquisition
sequence may be gated by either the hardware (AIGATE) signal or
software command register gate.

Rising-edge
polarity

Falling-edge
polarity

t

w

t

w

= 10 ns minimum

t

w

t

w

= 50-100 ns

«
...
87
88
89
90
91
...
»

Summary of Contents for AT-MIO/AI E Series

Page 1: ...Boards for the PC AT May 1996 Edition Part Number 320517E 01 Copyright 1994 1996 National Instruments Corporation All Rights Reserved Click here to comment on this document via the National Instruments website at http www natinst com documentation daq ...

Page 2: ...ia 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 T...

Page 3: ...OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in perf...

Page 4: ...to Get Started 1 2 Software Programming Choices 1 3 LabVIEW and LabWindows CVI Application Software 1 3 NI DAQ Driver Software 1 3 Register Level Programming 1 5 Optional Equipment 1 5 Custom Cabling 1 6 Unpacking 1 7 Chapter 2 Installation and Configuration Software Installation 2 1 Hardware Installation 2 1 Board Configuration 2 2 Bus Interface 2 2 Plug and Play 2 3 Switchless Data Acquisition 2...

Page 5: ...er 4 Signal Connections I O Connector 4 1 I O Connector Signal Descriptions 4 5 Analog Input Signal Connections 4 16 Types of Signal Sources 4 18 Floating Signal Sources 4 18 Ground Referenced Signal Sources 4 18 Input Configurations 4 18 Differential Connection Considerations DIFF Input Configuration 4 20 Differential Connections for Ground Referenced Signal Sources 4 21 Differential Connections ...

Page 6: ...TRIG Signal 4 42 UPDATE Signal 4 43 UISOURCE Signal 4 45 General Purpose Timing Signal Connections 4 46 GPCTR0_SOURCE Signal 4 46 GPCTR0_GATE Signal 4 47 GPCTR0_OUT Signal 4 47 GPCTR0_UP_DOWN Signal 4 48 GPCTR1_SOURCE Signal 4 48 GPCTR1_GATE Signal 4 49 GPCTR1_OUT Signal 4 50 GPCTR1_UP_DOWN Signal 4 51 FREQ_OUT Signal 4 52 Timing Specifications for Digital I O Ports A B and C 4 53 Mode 1 Input Tim...

Page 7: ...6E 1 and AT MIO 16E 2 Block Diagram 3 1 Figure 3 2 AT MIO 64E 3 Block Diagram 3 2 Figure 3 3 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram 3 3 Figure 3 4 AT MIO 16XE 10 Block Diagram 3 4 Figure 3 5 AT AI 16XE 10 Block Diagram 3 5 Figure 3 6 AT MIO 16XE 50 Block Diagram 3 6 Figure 3 7 Dither 3 12 Figure 3 8 Analog Trigger Block Diagram 3 16 Figure 3 9 Below Low Level Analog Triggering Mode 3 17 Fi...

Page 8: ...ion 4 33 Figure 4 15 SCANCLK Signal Timing 4 33 Figure 4 16 EXTSTROBE Signal Timing 4 34 Figure 4 17 TRIG1 Input Signal Timing 4 35 Figure 4 18 TRIG1 Output Signal Timing 4 35 Figure 4 19 TRIG2 Input Signal Timing 4 36 Figure 4 20 TRIG2 Output Signal Timing 4 37 Figure 4 21 STARTSCAN Input Signal Timing 4 38 Figure 4 22 STARTSCAN Output Signal Timing 4 38 Figure 4 23 CONVERT Input Signal Timing 4 ...

Page 9: ... 1 PC AT I O Address Map 2 4 Table 2 2 PC AT Interrupt Assignment Map 2 6 Table 2 3 PC AT 16 bit DMA Channel Assignment Map 2 7 Table 3 1 Available Input Configurations for the AT E Series 3 7 Table 3 2 Actual Range and Measurement Precision 3 8 Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 10 Table 4 1 I O Signal Summary AT MIO 16E 1 AT MIO 16E...

Page 10: ...ies boards are high performance multifunction analog digital and timing I O boards for the PC AT series computers Supported functions include analog input analog output digital I O and timing I O Organization of This Manual The AT MIO AI E Series User Manual is organized as follows Chapter 1 Introduction describes the AT E Series boards lists what you need to get started describes the optional sof...

Page 11: ...s or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations metric prefixes mnemonics and symbols The Index alphabetically lists topics covered in this manual including the page where you can find the topic Conventions Used in This Manual The following conventions are used in this manual bold Bold text den...

Page 12: ...XI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for ha...

Page 13: ...l Instruments document contains information you may find helpful Application Note 025 Field Wiring and Noise Considerations for Analog Signals Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact ...

Page 14: ...eries boards are the first completely switchless and jumperless data acquisition boards This feature is made possible by the National Instruments DAQ PnP bus interface chip that connects the board to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you to easily change the AT E Seri...

Page 15: ...hermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Detailed specifications of the AT E Series boards are in Appendix A Specifications What You Need to Get Started To set up and use your AT E Series board you will need the following One of the ...

Page 16: ...tion VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisitio...

Page 17: ...Q also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages LabVIEW or LabWindows CVI your application u...

Page 18: ...s flexible as register level programming and can save weeks of development time Optional Equipment National Instruments offers a variety of products to use with your AT E Series board including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 68 and 100 pin screw terminals Real Time System Integrati...

Page 19: ...using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended part numbers for connectors that mate to the I O connector on your AT E Series board Mating connectors and a backshell kit for making custom 68 pin cables are available from Na...

Page 20: ...handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in an...

Page 21: ...I DAQ release notes and follow the instructions given there for your operating system and LabVIEW If you are using LabWindows CVI refer to your LabWindows CVI release notes After you have installed LabWindows CVI refer to your NI DAQ release notes and follow the instructions given there for your operating system and LabWindows CVI If you are a register level programmer refer to the AT MIO E Series...

Page 22: ...lug in and turn on your computer The AT E Series board is installed You are now ready to install and configure your software Board Configuration Due to the DAQ PnP features the AT E Series boards are completely software configurable Two types of configuration must be performed on the AT E Series boards bus related configuration and data acquisition related configuration Bus related configuration i...

Page 23: ...s Data Acquisition You can use an AT E Series board in a non Plug and Play system as a switchless DAQ board A non Plug and Play system is a system in which the Configuration Manager has not been installed and which does not contain any non National Instruments Plug and Play products You use a configuration utility to enter the base address DMA and interrupt selections and the application software ...

Page 24: ...s boards can use interrupt channels 3 4 5 7 10 11 12 and 15 These selections are all software configured and do not require you to manually change any settings on the board The following tables provide information concerning possible conflicts when configuring your AT E Series board Table 2 1 PC AT I O Address Map I O Address Range Hex Device 100 to 1EF 1F0 to 1F8 IBM PC AT Fixed Disk 200 to 20F P...

Page 25: ...AT Parallel Printer Port 1 LPT1 380 to 38C SDLC Communications 380 to 389 Bisynchronous BSC Communications alternate 390 to 393 Cluster Adapter 0 394 to 39F 3A0 to 3A9 BSC Communications primary 3AA to 3AF 3B0 to 3BF Monochrome Display Parallel Printer Adapter 0 3C0 to 3CF Enhanced Graphics Adapter VGA 3D0 to 3DF Color Graphics Monitor Adapter VGA 3E0 to 3EF 3F0 to 3F7 Diskette Controller 3F8 to 3...

Page 26: ...ork default PC Network Alternate default 8 Real Time Clock 7 Parallel Port 1 LPT1 6 Diskette Drive Controller Fixed Disk and Diskette Drive Controller 5 Parallel Port 2 LPT2 PC DIO 24 default Lab PC PC default 4 Serial Port 1 COM1 BSC BSC Alternate 3 Serial Port 2 COM2 BSC BSC Alternate Cluster primary PC Network PC Network Alternate WD EtherCard default 3Com EtherLink default 2 IRQ 8 15 Chain fro...

Page 27: ...User Manual Note EISA computers also have channels 0 3 available as 16 bit DMA channels Table 2 3 PC AT 16 bit DMA Channel Assignment Map Channel Device 7 AT MIO 16 series default 6 AT MIO 16 series default AT DIO 32F default 5 AT DIO 32F default 4 Cascade for DMA Controller 1 channels 0 through 3 ...

Page 28: ...onfiguration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Analog Trigger Circuitry 2 Trigger Level DACs 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 DAC FI...

Page 29: ... Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Analog Trigger Circuitry 2 Trigger Level DACs 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 32 32 DAC FIFO 8 Data 16 AI Control Data 16 Analog Input Control EEPROM ...

Page 30: ...I O 8 12 Bit Sampling A D Converter EEPROM Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8255 DIO Port 8 ...

Page 31: ...er Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8 AI Control Analog Input Control EEPROM Control DMA Interface DAQ PnP DAQ STC Bus Interface Plug and Play Analog Out...

Page 32: ...ogrammable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8 AI Control Analog Input Control EEPROM Control DMA Interface DAQ PnP DAQ STC Bus Interface Plug and Play Analog Output Co...

Page 33: ...e single ended input configurations use up to 16 channels 64 channels on the AT MIO 64E 3 The DIFF input configuration uses up to eight channels 32 channels on the AT MIO 64E 3 Input modes are Timing PFI Trigger I O Connector 3 2 RTSI Bus AT I O Channel Digital I O 8 16 Bit Sampling A D Converter EEPROM Configuration Memory Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches An...

Page 34: ... where Vref is a positive reference voltage Bipolar input means that the input voltage range is between Vref 2 and Vref 2 The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V Table 3 1 Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DI...

Page 35: ...re the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 2 44 mV 1 22 mV 488 28 µV 244 14 µV 122 07 µV 48 ...

Page 36: ...ur AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 analog input circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in your scan list and you are using NI DAQ then NI DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured The software programmable gain on these boards increases their overall flexib...

Page 37: ... However if the signal is negative or equal to zero inaccurate readings will occur if you use unipolar input polarity Table 3 3 Actual Range and Measurement Precision AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 0 2 0 5 02 10 0 20 02 50 02 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 152 59 µV 7...

Page 38: ... measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise You enable and disable the dither circuitry through software Figure 3 7 illustrates the effect of dither on signal acquisition Figure 3 7a shows a small 4 LSB sine wave acquired with dither off The quantization of the ADC is...

Page 39: ...s independent of the selected gain even at the maximum sampling rate The settling time for the high channel count and very high speed boards is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 LSBs LSBs LSBs LSBs 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 ...

Page 40: ...µs for the circuitry to settle this much For a 16 bit board to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 µs for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling ...

Page 41: ...ut Reference Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 AT MIO 16DE 10 only You can connect each D A converter DAC to the AT E Series board internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for th...

Page 42: ...t is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output of the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate i...

Page 43: ... AT AI 16XE 10 Note The PFI0 TRIG1 pin is a high impedance input Therefore it is susceptible to cross talk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 10 kΩ source impedance if you plan to enable this input via software Figure 3 8 Analog Trigger Block Di...

Page 44: ...ode the trigger is generated when the signal value is greater than highValue LowValue is unused Figure 3 10 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue Figure 3 11 Inside Region Analog Triggering Mode lowValue Trigger highValue Trigger highValue Trigger lowValue ...

Page 45: ...3 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquir...

Page 46: ...e general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other boards or external circuitry Your AT E Series board uses the RTSI bus for interconnecting timing signals between boards and the Programmable Function Input PFI pins on the I...

Page 47: ...er in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple...

Page 48: ...e received over the RTSI bus In addition if you configure the board to use the internal timebase you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the board as the primary frequency source The default configuration at startup is ...

Page 49: ...Connection Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3 15 RTSI Bus Connector switch RTSI Switch Clock Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz ...

Page 50: ...connect your board to 68 pin accessories and with the R1005050 ribbon cable you can connect your board to 50 pin accessories I O Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Figure 4 2 shows the pin assignments for the 100 pin I O connector on the AT MIO 64E 3 Figure 4 3 sh...

Page 51: ... V DGND PFI1 TRIG2 PFI0 TRIG1 DGND DGND 5 V DGND DIO6 DIO1 DGND DIO4 EXTREF DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH...

Page 52: ...R0_OUT ACH55 PFI9 GPCTR0_GATE ACH62 PFI8 GPCTR0_SOURCE ACH54 PFI7 STARTSCAN ACH61 PFI6 WFTRIG ACH53 PFI5 UPDATE ACH60 GPCTR1_OUT ACH52 PFI4 GPCTR1_GATE ACH59 PFI3 GPCTR1_SOURCE ACH51 PFI2 CONVERT ACH58 PFI1 TRIG2 ACH50 PFI0 TRIG1 ACH57 EXTSTROBE ACH49 SCANCLK ACH56 5 V ACH48 5 V ACH47 DGND ACH39 DIO7 ACH46 DIO3 ACH38 DIO6 ACH45 DIO2 ACH37 DIO5 ACH44 DIO1 ACH36 DIO4 AIGND DIO0 AISENSE2 DGND ACH43 A...

Page 53: ...57 6 56 5 55 4 54 3 53 2 52 1 51 FREQ_OUT GND GPCTR0_OUT 5 V PFI9 GPCTR0_GATE GND PFI8 GPCTR0_SOURCE PA0 PFI7 STARTSCAN GND PFI6 WFTRIG PA1 PFI5 UPDATE GND GPCTR1_OUT PA2 PFI4 GPCTR1_GATE GND PFI3 GPCTR1_SOURCE PA3 PFI2 CONVERT GND PFI1 TRIG2 PA4 PFI0 TRIG1 GND EXTSTROBE PA5 SCANCLK GND 5 V PA6 5 V GND DGND PA7 DIO7 GND DIO3 PB0 DIO6 GND DIO2 PB1 DIO5 GND DIO1 PB2 DIO4 GND DIO0 PB3 DGND GND AOGND ...

Page 54: ...hannels ACH 0 15 in NRSE configuration AISENSE2 AIGND Input Analog Input Sense AT MIO 64E 3 only This pin serves as the reference node for any of channels ACH 16 63 in NRSE configuration DAC0OUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 This pin is not available on the AT AI 16XE 10 DAC1OUT AOGND Output Analog Channel 1 Output This pin sup...

Page 55: ... This output can be toggled under software control to latch signals or trigger events on external devices PFI0 TRIG1 DGND Input Output PFI0 Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the An...

Page 56: ...rpose counter 1 output PFI5 UPDATE DGND Input Output PFI5 Update As an input this is one of the PFIs As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input Output PFI6 Waveform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed analog output sequences a low t...

Page 57: ...rpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output Table 4 1 I O Signal Summary AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Signal Name Drive Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH 0 63 AI 100 GΩ in parallel with 100 pF 25 15 200 pA AISENSE AISENSE2 AI 100 GΩ in parallel with 100 p...

Page 58: ... pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI7 STARTSCAN DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu 1DIO 6 7 are also pulled down with a ...

Page 59: ...Short circuit to ground 5 at 10 5 at 10 15 V µs DAC1OUT AO 0 1 Ω Short circuit to ground 5 at 10 5 at 10 15 V µs EXTREF AI 10 kΩ 35 25 AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu1 PA 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kΩ pu PB 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kΩ pu PC 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 1...

Page 60: ... GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu 1DIO 6 7 are also pulled down with a 50 kΩ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kΩ ...

Page 61: ...rt circuit to ground 5 at 10 5 at 10 5 V µs DAC1OUT AO 0 1 Ω Short circuit to ground 5 at 10 5 at 10 5 V µs AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI0 TRIG1 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 4 75 kΩ pu PFI1 TRIG2 DIO Vcc...

Page 62: ...I9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kΩ pullup and pulldown resistors is very large Actual value may range between 17 kΩ and 100 kΩ Table 4 3 I O Signal Summa...

Page 63: ...nd 5 at 10 5 at 10 2 V µs DAC1OUT AO 0 1 Ω Short circuit to ground 5 at 10 5 at 10 2 V µs AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu1 SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI0 TRIG1 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI1 TRIG2 DIO Vcc 0 5 3 5 at Vcc 0 4...

Page 64: ...O Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu 1DIO 6 7 are also pulled down with a 50 kΩ resistor AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kΩ pullup and pulldown resistors is very large Actual value may range between 17 kΩ an...

Page 65: ...23 32 39 48 55 are routed to the positive input of the PGIA and signals connected to ACH 8 15 24 31 40 47 56 63 are routed to the negative input of the PGIA Warning Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the AT E Series board and the PC National Instruments is NOT liable for any damages resulting fro...

Page 66: ...plied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the board Your AT E Series board A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the board If you have a floating source you should reference the signal to ground by using the RSE input mod...

Page 67: ...e common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT E Series board assuming that the PC is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power sy...

Page 68: ...eferenced NRSE Floating Signal Source Not Connected to Building Ground Grounded Signal Source Examples Ungrounded Thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in instruments with nonisolated outputs V1 ACH V1 ACH ACH See text for information on bias resistors See text for information on bias resistors R Signal Source Type ACH AIGND V1 ACH AIGND NOT RECOMMEN...

Page 69: ...ses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available up to 32 channels on the AT MIO 64E 3 You should use differential input connections for any channel that meets any of the following conditions The input signal is low level less than 1 V The leads connecting the...

Page 70: ...ifferential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT E Series board ground shown as Vcm in Figure 4 6 Ground Referenced Signal Source Common Mode Noise and Ground Potential Input Multiplexers AISENSE Instrumentation Amplifier Vm Meas...

Page 71: ...do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as...

Page 72: ...f the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 7 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kΩ and each of the two ...

Page 73: ...th other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the AT E Series board channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT E Series board provid...

Page 74: ...d to the positive input of the AT E Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the AT E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is r...

Page 75: ...ences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as long as V in and V in are both within 11 V of AIGND The AT MIO 16XE 50 has the additional restriction that V in V in added to the gain times V in V in must be wit...

Page 76: ...re each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference You cannot use an external analog output reference with the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Analog output configuration options ar...

Page 77: ...the output voltage Digital I O Signal Connections The digital I O signals are DIO 0 7 and DGND DIO 0 7 are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA 0 7 PB 0 7 and PC 0 7 You can configure each port for bo...

Page 78: ...s signal connections for three typical digital I O applications Figure 4 11 Digital I O Connections Figure 4 11 shows DIO 0 3 configured for digital input and DIO 4 7 configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and...

Page 79: ...for any damages resulting from such signal connections All external control over the timing of your AT E Series board is routed through the 10 programmable function inputs labeled PFI0 through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many data acq...

Page 80: ... I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin You must be careful not to drive a PFI signal externally when it is configured as an output As ...

Page 81: ...g controlled These requirements are listed later in this chapter Data Acquisition Timing Connections The data acquisition timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered data acquisition sequence is shown in Figure 4 13 Pretri...

Page 82: ...ut multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 15 shows the timing for the SCANCLK signal Figure 4 15 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external de...

Page 83: ...ct any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 64E 3 support analog triggering on the PFI0 TRIG1 pin See Chapter 3 for more information on ...

Page 84: ... also uses the TRIG1 signal to initiate pretriggered data acquisition operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered data acquisition operation Rising edge polarity Falling edge polarity tw tw 10 ns minimum tw tw 50 100 ns ...

Page 85: ...fter the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the board will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and afte...

Page 86: ...ing or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter is started if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a puls...

Page 87: ... output timing requirements for the STARTSCAN signal Figure 4 21 STARTSCAN Input Signal Timing Figure 4 22 STARTSCAN Output Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum tw 50 100 ns a Start of Scan toff toff 10 ns minimum Start Pulse CONVERT STARTSCAN STARTSCAN b Scan in Progress Two Conversions per Scan tw ...

Page 88: ...re inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 13 and 4 14 for the relationship of CONVERT to the data a...

Page 89: ...nversion period The sample interval counter on the AT E Series board normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in readiness for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT s...

Page 90: ...ge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input t...

Page 91: ... as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As...

Page 92: ...e detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the upd...

Page 93: ...eparate the UPDATE pulses with enough time that new data can be written to the DAC latches The AT E Series board UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when...

Page 94: ...as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 30 shows the timing requirements for the UISOURCE signal Figure 4 30 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the...

Page 95: ...y PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR0_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup Figure 4 31 shows the timing requirements for the GPCTR0_SOURCE sig...

Page 96: ...an output the GPCTR0_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 32 shows the timing requirements for the GPCTR0_GATE signal Figure 4 32 GPCTR0_GATE Signal Timing in Edge Detection Mode GPCTR0_OUT Signal This signal is available only ...

Page 97: ...the DIO6 pin free for general use GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the ...

Page 98: ... which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating ...

Page 99: ...pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 36 shows the timing requirements for the GPCTR1_OUT signal Figure 4 36 GPCTR1_OUT Signal Timing Rising edge polarity Fall...

Page 100: ...can control the up down functionality and leave the DIO7 pin free for general use Figure 4 37 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your AT E Series board Figure 4 37 GPCTR Timing Summary SOURCE V IH V IL V IH V IL tsc tsp tsp tgsu tgh tgw GATE tout OUT V OH V OL sc t t t t t t 50 ns minimum sp 23 ns minimum ...

Page 101: ...ter the active edge of the source signal If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are refere...

Page 102: ... it is programmed In mode 0 port C is considered two 4 bit I O ports In modes 1 and 2 port C is used for status and handshaking signals with two or three additional I O bits Table 4 5 summarizes the signal assignments of port C for each programmable mode Table 4 5 Port C Signal Assignments Programming Mode Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Mode 0 I O I O I O I O I O I O I O I O Mode ...

Page 103: ...t A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16DE 10 OBF output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port INTR output Interrupt Request This signal becomes high...

Page 104: ...specifications for an input transfer in Mode 1 Figure 4 38 Mode 1 Input Timing Name Description Minimum Maximum T1 STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 ...

Page 105: ...re the timing specifications for an output transfer in Mode 1 Figure 4 39 Mode 1 Output Timing Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 ...

Page 106: ... Figure 4 40 Mode 2 Bidirectional Timing Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OBF INTR ACK STB IBF...

Page 107: ...signals traveling through areas with large magnetic fields or high electromagnetic interference Route signals to the board carefully Keep cabling away from noise sources The most common noise source in a PC data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your AT E Series ...

Page 108: ...astest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your AT E Series board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored...

Page 109: ...ime or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration Your AT E Series board has an onboard calibration reference to ensure the accuracy of ...

Page 110: ...should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In thi...

Page 111: ...T MIO 64E 3 Analog Input Input Characteristics Number of channels AT MIO 16E 1 AT MIO 16E 2 16 single ended or 8 differential software selectable AT MIO 64E 3 64 single ended or 32 differential software selectable Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Max sampling rate AT MIO 16E 1 1 25 MS s guaranteed AT MIO 16E 2 AT MIO 64E 3 500 kS s guaranteed Throughput to system ...

Page 112: ...d off Inputs protected ACH 0 63 AISENSE AISENSE2 FIFO buffer size AT MIO 16E 1 8 192 samples AT MIO 16E 2 AT MIO 64E 3 2 048 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Configuration memory size 512 words Input signal ranges Board Gain Software Selectable Board Range Software Selectable Bipolar Unipolar 0 5 10 V 1 5 V 0 to 10 V 2 2 5 V 0 to 5 V 5 ...

Page 113: ...r before calibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GΩ in parallel with ...

Page 114: ...me for full scale step Gain Accuracy 0 012 0 5 LSB 0 024 1 LSB 0 098 4 LSB AT MIO 16E 1 0 5 2 µs typ 3 µs max 1 5 µs typ 2 µs max 1 5 µs typ 2 µs max 1 1 5 µs typ 2 µs max 1 3 µs typ 1 5 µs max 1 1 µs typ 1 3 µs max 2 to 50 2 µs typ 3 µs max 1 5 µs typ 2 µs max 0 9 µs typ 1 µs max 100 2 µs typ 3 µs max 1 5 µs typ 2 µs max 1 µs typ 1 5 µs max AT MIO 16E 2 All 2 µs typ 4 µs max 1 9 µs typ 2 µs max 1...

Page 115: ...t Pregain 5 µV C Postgain 240 µV C Gain temperature coefficient 20 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm System noise LSBrms not including quantization Gain Noise dither off Noise dither on AT MIO 16E 1 0 5 to 10 0 25 0 5 20 0 4 0 6 50 0 5 0 7 100 0 8 0 9 AT MIO 16E 2 AT MIO 64E 3 0 5 to...

Page 116: ...t 2 channel 300 625 kS s system dependent Type of DAC Double buffered multiplying FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monoton...

Page 117: ...Protection Short circuit to ground Power on state 0 V External reference input Range 11 V Overvoltage protection 25 V powered on 15 V powered off Input impedance 10 kΩ Bandwidth 3 dB 1 MHz Dynamic Characteristics Settling time for full scale step 3 µs to 0 5 LSB accuracy Slew rate 20 V µs Noise 200 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 200 mV Reglitc...

Page 118: ...er of channels 8 input output Compatibility TTL CMOS Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scalers 4 bits Compatibility TTL CMOS Digital logic levels Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current Vin 0 V 320 µA Input high...

Page 119: ...ulse duration 10 ns in edge detect mode Data transfers DMA interrupts programmed I O DMA modes Single transfer Triggers Analog Trigger Source ACH 0 63 PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidth 3 dB 1 5 MHz internal 7 MHz external External input PFI0 TRIG1 Impedance 10 kΩ Coupling DC...

Page 120: ...SI Trigger lines 7 Bus Interface Type Slave Power Requirement 5 VDC 5 1 0 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector AT MIO 16E 1 AT MIO 16E 2 68 pin male SCSI II type AT MIO 64E 3 100 pin female 0 050 D type Environment Operating temperature 0 to 55 C Storage temperature 55 to 150 C Relati...

Page 121: ...ling rate 100 kS s guaranteed Input coupling DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 35 V powered on 25 V powered off Inputs protected ACH 0 15 AISENSE FIFO buffer size 512 samples Input signal ranges Board Gain Software Selectable Board Range Software Selectable 5 V 0 10 V 0 5 10 V 1 5 V 0 to 10 V 2 2 5 V 0 to 5 V 5 1 V 0 to ...

Page 122: ...e calibration 24 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration Gain 1 0 01 of reading max Before calibration 2 0 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 05 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GΩ in parallel with 50 pF Po...

Page 123: ...t 20 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate 100 kS s Type of DAC Double buffered multiplying FIFO buffer size None System noise not including quantization Gain Noise 0 5 to 10 0...

Page 124: ...1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error relative to external reference 0 to 0 5 of output max not adjustable Voltage Output Ranges 10 V 0 to 10 V EXTR...

Page 125: ... to 0 5 LSB accuracy Slew rate 15 V µs Noise 200 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude 100 mV Duration 3 µs Stability Offset temperature coefficient 50 µV C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stab...

Page 126: ...e 0 V 0 8 V Input high voltage 2 V 5 V Input low current Vin 0 V 320 µA Input high current Vin 5 V 10 µA Output low voltage IOL 24 mA 0 4 V Output high voltage IOH 13 mA 4 35 V PA 0 7 PB 0 7 PC 0 7 Level Min Max AT MIO 16DE 10 only Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current Vin 0 V 60 µA Input high current Vin 5 V 10 µA Output low voltage IOL 2 5 mA 0 4 V Output high ...

Page 127: ...ion Counter timers 24 bits Frequency scalers 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers DMA interrupts programmed I O DMA modes Single transfer Triggers Digita...

Page 128: ... 5 0 7 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector AT MIO 16E 10 68 pin male SCSI II type AT MIO 16DE 10 100 pin female 0 050 D type Environment Operating temperature 0 to 55 C Storage temperature 55 to 150 C Relative humidity 5 to 90 noncondensing ...

Page 129: ...put coupling DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH 0 15 AISENSE FIFO buffer size 512 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Input signal ranges Board Gain Software Selectable Board Range Software Selectable Bipolar Unipolar 1 10 0 ...

Page 130: ...x Postgain error after calibration 76 µV max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 1 200 ppm of reading Amplifier Characteristics Input impedance Normal powered on 100 GΩ in parallel with 100 pF Powered off 820...

Page 131: ...s bipolar 0 8 LSB rms unipolar Gain 20 0 7 LSB rms bipolar 1 1 LSB rms unipolar Gain 50 1 1 LSB rms bipolar 2 0 LSB rms unipolar Gain 100 2 0 LSB rms bipolar 3 8 LSB rms unipolar Dynamic range 91 7 dB full scale input with gain 1 to 10 Crosstalk 70 dB max DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 5 µV C Postgain 120 µV C Gain temperature coeffic...

Page 132: ...fers DMA interrupts programmed I O DMA modes Single transfer demand transfer Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max DNL 1 LSB max Monotonicity 16 bits guaranteed Offset error After calibration 305 µV max Before calibration 20 mV max Gain error relative to internal reference After calibration 30 5 ppm max Before calibration 2 000 ppm max Voltage Output Range 10 V 0 to ...

Page 133: ...ature coefficient 7 5 ppm C Onboard calibration reference Level 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Digital I O Number of channels 8 input output Compatibility TTL CMOS Power on state Input High Z Data transfers Programmed I O Digital logic levels Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low ...

Page 134: ...er timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes Single transfer Triggers Analog Trigger Source ACH 0 15 PFI0 TRIG1 Level Full scale internal 10 V external Slope Positive or negative softw...

Page 135: ...led 35 V powered off Accuracy 1 of full scale range Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min RTSI Trigger Lines 7 Bus Interface Type Slave Power Requirement 5 VDC 5 1 2 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector 68 pin male SCSI II type Environ...

Page 136: ...m working voltage signal common mode The average voltage of each differential pair should remain within 8 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH 0 15 AISENSE FIFO buffer size 512 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Configuration memory size 512 words Input signal ranges Board Gain Software ...

Page 137: ...efore calibration 4 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2250 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 2 10 100 ppm of reading Gain 100 250 ppm of reading Amplifier Characteristics Input impedance Normal powered on 7 GΩ in parallel with 100 pF Powered off 820 Ω min Overload 820 Ω min Input bia...

Page 138: ...emperature coefficient Pregain 1 µV C Postgain 12 µV C Gain temperature coefficient 5 ppm C Onboard calibration reference Level 5 000 V 2 0 mV actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 15 ppm Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate 20 kS s Type of DAC Double buffered FIFO buffer size...

Page 139: ...g DC Output impedance 0 1 Ω max Current drive 5 mA Protection Short circuit to ground Power on state 0 V 85 mV Dynamic Characteristics Settling time for full scale step 50 µs to 0 5 LSB accuracy Slew rate 2 V µs Noise 40 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude 30 mV Duration 10 µs Stability Offset temperature coefficient 25 µV C Gain temperature coefficient 15 ppm C Onboar...

Page 140: ...1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Digital logic levels Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current 320 µA...

Page 141: ... Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min RTSI Trigger Lines 7 Bus Interface Type Slave Power Requirement 5 VDC 5 0 75 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector 68 pin male SCSI II type Environment Operating temperature 0 to 55 C Storage temperature 5...

Page 142: ... E Series boards Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 or R6868 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 68 pin connectors available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 ...

Page 143: ...ND DGND 5 V DGND DIO6 DIO1 DGND DIO4 EXTREF DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 35 2 36 3 37 4 38...

Page 144: ...2 68 Pin DIO Connector Pin Assignments N C N C N C N C N C N C N C N C N C 5 V PA0 GND GND PA3 GND GND PA6 GND GND PB1 GND GND PB4 PB5 GND PB7 PC0 GND PC2 PC3 GND PC5 PC6 GND N C N C N C N C N C N C N C N C N C GND GND PA1 PA2 GND PA4 PA5 GND PA7 PB0 GND PB2 PB3 GND GND PB6 GND GND PC1 GND GND PC4 GND GND PC7 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17...

Page 145: ...N C N C N C N C ACH 55 ACH 54 ACH 61 ACH 52 ACH 51 ACH 58 ACH 49 ACH 48 ACH 47 ACH 38 ACH 37 ACH 44 AIGND ACH 35 ACH 34 ACH 41 ACH 32 ACH 23 ACH 30 ACH 21 ACH 20 ACH 27 ACH 18 ACH 17 ACH 24 N C N C N C N C N C N C N C N C N C ACH 63 ACH 62 ACH 53 ACH 60 ACH 59 ACH 50 ACH 57 ACH 56 ACH 39 ACH 46 ACH 45 ACH 36 AISENSE2 ACH 43 ACH 42 ACH 33 ACH 40 ACH 31 ACH 22 ACH 29 ACH 28 ACH 19 ACH 26 ACH 25 ACH ...

Page 146: ...050 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 Figure B 4 50 Pin MIO Connector Pin Assignments GPCTR0_OUT PFI8 GPCTR0_SOURCE PFI6 WFTRIG GPCTR1_OUT PFI3 GPCTR1_SOURCE PFI1 TRIG2 EXTSTROBE 5 V DGND DIO3 DIO2 DIO1 DIO0 AOGND DAC1OUT AISENSE ACH7 ACH6 ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 AIGND FREQ_OUT PFI7 STARTSCAN PFI5 UPDATE PFI2 CONVERT PFI0 TRIG1 SCANCLK 5 V PFI9 GPCTR0_GATE PFI4 GPCTR1_GA...

Page 147: ... the R1005050 cable assembly with the AT MIO 16DE 10 Figure B 5 50 Pin DIO Connector Pin Assignments 5 V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 ...

Page 148: ... Figure B 6 50 Pin Extended Analog Input Connector Pin Assignments ACH55 ACH54 ACH53 ACH52 ACH51 ACH50 ACH49 ACH48 ACH39 ACH38 ACH37 ACH36 AISENSE2 ACH35 ACH34 ACH33 ACH32 ACH23 ACH22 ACH21 ACH20 ACH19 ACH18 ACH17 ACH16 ACH63 ACH61 ACH60 ACH58 ACH57 ACH56 ACH47 ACH62 ACH59 ACH46 ACH45 ACH44 AIGND ACH43 ACH42 ACH41 ACH40 ACH31 ACH30 ACH29 ACH28 ACH27 ACH26 ACH25 ACH24 49 50 47 48 45 46 43 44 41 42 ...

Page 149: ...6 bit counters Analog output three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 µs With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New ca...

Page 150: ...a field for base I O address type in the desired base I O address 0x180 200 220 240 280 and 300 are typical base addresses 7 What jumpers should I be aware of when configuring my AT E Series board The AT E Series boards do not contain any jumpers they are also switchless 8 Which National Instruments manual should I read first to get started using DAQ software If you are using LabVIEW Chapter 1 of ...

Page 151: ... are using You may be more limited in the functionality of the board usually regarding high speed acquisition but you should at least be able to use basic functionality for all boards in the system 13 How can I select an AT E Series board as my device type in DAQCONF or WDAQCONF First make sure your board is plugged into your computer The DAQCONF and WDAQCONF utilities scan your system for any AT ...

Page 152: ...pass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal The AT MIO 16E 1 AT MIO 16E 2 and the AT MIO 64E 3 boards have built in reglitchers which can be enabled through software on their analog output channels See the Analog Output Reglitch Selection section in Chapter 3 for more information about reglitching 17 Can I synchronize a one c...

Page 153: ...WFM_Group_Control with operation set to 1 start If you are using LabVIEW invoke AO Control VI with control code set to 0 start Timing and Digital I O 18 What types of triggering can be implemented in hardware on my AT E Series board Digital triggering is supported by hardware on every AT E Series MIO board In addition the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 supp...

Page 154: ...base selections are different the DAQ STC counters are 24 bit counters unlike the 16 bit counters on boards without the DAQ STC If you are using NI DAQ language interface LabWindows or LabWindows CVI the answer is no the counter time applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR...

Page 155: ...lect_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level...

Page 156: ...ommon Questions AT MIO AI E Series User Manual C 8 National Instruments Corporation a 50 kΩ pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state ...

Page 157: ...port through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use ...

Page 158: ... National Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9 879 9422 03 9 879 9179 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 519 622 9310 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 90 527 2321 90 502 2930 France 1 48 14 24 24...

Page 159: ..._________________________________________________________________ National Instruments hardware product model___________ Revision ________________________ Configuration ___________________________________________________________________ National Instruments software product____________________________ Version____________ Configuration _______________________________________________________________...

Page 160: ...______________________________________________________ Other Products Computer Model ______________________________________________________________ Microprocessor _______________________________________________________________ Clock Frequency ______________________________________________________________ Type of Video Board Installed ___________________________________________________ Operating Sy...

Page 161: ...____________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ ___...

Page 162: ...es User Manual Symbols percent plus or minus degrees per positive of or plus negative of or minus Ω ohms square root of 5V 5 VDC source signal Prefix Meaning Value p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Glossary ...

Page 163: ...ND analog input ground signal AISENSE analog input sense signal AISENSE2 analog input sense 2 signal ANSI American National Standards Institute AOGND analog output ground signal ASIC application specific integrated circuit B BIOS basic input output system or built in operating system C C Celsius CalDAC calibration DAC CMOS complementary metal oxide semiconductor CMRR common mode rejection ratio CO...

Page 164: ...data acquisition DC direct current DGND digital ground signal DIFF differential mode DIO digital input output DMA direct memory access DNL differential nonlinearity E EEPROM electrically erasable programmable read only memory EISA Extended Industry Standard Architecture EXTREF external reference signal EXTSTROBE external strobe signal F FIFO first in first out FREQ_OUT frequency output signal ft f...

Page 165: ...utput signal GPCTR1_OUT general purpose counter 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR1_SOURCE general purpose counter 1 clock source signal H h hour hex hexadecimal Hz hertz I I O input output IOH current output high IOL current output low ISA Industry Standard Architecture L LASTCHAN last channel bit LSB least significant bit M MB megabytes of memory MI...

Page 166: ... Programmable Function Input PGIA Programmable Gain Instrumentation Amplifier ppm parts per million R rms root mean square RSE referenced single ended mode RTD resistive temperature device RTSI Real Time System Integration S s seconds S samples SCANCLK scan clock signal SCXI Signal Conditioning eXtensions for Instrumentation SE single ended inputs SISOURCE SI counter clock signal ...

Page 167: ...stortion TRIG trigger signal TTL transistor transistor logic U UI update interval UISOURCE update interval counter clock signal UPDATE update signal V V volts VDC volts direct current VIH volts input high VIL volts input low Vin volts in VOH volts output high VOL volts output low Vref reference voltage W WFTRIG waveform generation trigger signal ...

Page 168: ...0 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 differentialconnectionsforfloatingsignal sources 4 22 to 4 23 AISENSE signal analog input connections 4 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 AISENSE2 signal analog input connections 4 ...

Page 169: ...ications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 to A 7 dynamic characteristics A 7 output characteristics A 6 stability A 7 to A 8 transfer characteristics A 6 to A 7 voltage output A 7 AT MIO 16E 10 and AT MIO 16DE 10 dynamic characteristics A 15 output characteristics A 13 to A 14 stability A 15 transfer characteristics A 14 voltage output A 14 to A 15 AT MIO 16XE 10 dynamic characterist...

Page 170: ...iring considerations 4 58 optional equipment 1 5 calibration 5 1 to 5 3 adjusting for gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5 2 self calibration 5 2 charge injection 3 13 clocks board and RTSI 3 21 commonly asked questions See questions about AT E series boards common mode signal rejection 4 26 configuration See also input configurations base I O addre...

Page 171: ...table 3 7 description 4 20 ground referenced signal sources 4 21 nonreferenced or floating signal sources 4 22 to 4 23 single ended connections 4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use 4 20 digital I O common questions about C 5 to C 8 operation 3 19 signal connections 4 28 to 4 29 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 AT MIO 16E 1...

Page 172: ... AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 31 environmental noise avoiding 4 58 equipment optional 1 5 EXTREF signal analog output reference connections 4 27 to 4 28 analog output reference selection 3 14 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 5 EXTSTROBE signal AT MIO 1...

Page 173: ... 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 waveform generation timing connections 4 50 GPCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 ground referenced signal sources description 4 18 differential connections 4 21 single ended connections NRSE configuration 4 25 H hardware installation 2 1 to 2 2 hardware overvie...

Page 174: ...g signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 input polarity and range 3 7 to 3 10 AT MIO 16E 1 AT MIO 16E 2 AT MIO 643 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 to 3 8 actual range and measurement precision table 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 9 to 3 10 AT MIO 16XE 10 AT MIO 16XE 50 actual range and measurement precision table 3 10 mix...

Page 175: ... 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI1 TRIG2 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI2 CONVERT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 1...

Page 176: ...e 4 15 description table 4 8 PFIs programmable function inputs 4 31 to 4 32 common questions about C 7 C 7 to C 8 overview 4 30 signal routing 3 19 to 3 20 PGIA programmable gain instrumentation amplifier common mode signal rejection 4 26 differential connections floating signal sources 4 22 to 4 23 ground referenced signal sources 4 21 physical specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO ...

Page 177: ...0 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 33 settling time 3 12 to 3 13 C 1 to C 2 signal connections analog input 4 16 to 4 17 analog output 4 27 to 4 28 digital I O 4 28 to 4 29 field wiring considerations 4 58 I O connector 4 1 to 4 15 exceeding maximum ratings warning 4 1 4 16 4 29 I O signal summary table AT M...

Page 178: ...4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use 4 24 SISOURCE signal 4 41 to 4 42 software programming choices LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 5 register level programming 1 5 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog input A 1 to A 5 amplifier characteristics A 3 dynamic characteristics A 4 to A 5 input char...

Page 179: ... 24 to A 25 analog trigger A 24 to A 25 digital trigger A 25 RTSI A 25 AT MIO 16XE 50 analog input A 26 to A 28 amplifier characteristics A 27 dynamic characteristics A 27 to A 28 input characteristics A 26 stability A 28 transfer characteristics A 27 analog output A 28 to A 29 dynamic characteristics A 29 output characteristics A 28 stability A 29 transfer characteristics A 28 to A 29 voltage out...

Page 180: ...PCTR1_SOURCE signal 4 48 to 4 49 GPCTR1_UP_DOWN signal 4 51 to 4 52 programmable function input connections 4 31 to 4 32 waveform generation timing connections 4 42 to 4 45 UNISOURCE signal 4 45 UPDATE signal 4 43 to 4 44 WFTRIG signal 4 42 to 4 43 timing I O specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 to A 9 AT MIO 16E 10 and AT MIO 16DE 10 A 17 AT MIO 16XE 10 and AT AI 16XE 10 ...

Page 181: ... 3 10 mixing bipolar and unipolar channels note 3 9 unipolar output 3 14 to 3 15 unpacking AT E series boards 1 7 UPDATE signal timing connections 4 43 to 4 44 V VCC signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 voltage output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A ...

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