National Instruments AT-MIO-16D, User Manual

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Configuration and Installation Chapter 2
AT-MIO-16D User Manual 2-36 © National Instruments Corporation
In Figure 2-32, port A is configured for digital output, and port B is configured for digital input.
Digital input applications include receiving TTL signals and sensing external device states such as
the state of the switch in Figure 2-32. Digital output applications include sending TTL signals and
driving external devices such as the LED shown in Figure 2-32.
Power Connections
Pins 34 and 35 of the MIO-16 I/O connector p5 V from the PC AT power supply. These
pins are referenced to DIG GND and can be used to power external digital circuitry.
Power rating: 1 A at +5 V
±
10%
Warning: These +5 V power pins should not be directly connected to analog or digital ground
or to any other voltage source on the AT-MIO-16D or any other device. Doing so
can damage the AT-MIO-16D and the PC AT. National Instruments is not liable for
damages resulting from such a connection. A spare MIO-16 fuse is provided in case
the power rating is inadvertently exceeded. You should use this fuse only after the
cause of the initial problem is known, so as not to blow the spare fuse as well.
Timing Connections
Pins 36 through 50 of the MIO-16 I/O connector are connections for timing I/O signals. Pins 36
through 40 carry signals used for data acquisition timing. These signals are explained under the
Data Acquisition Timing Connections section later in this chapter. Pins 41 through 50 carry
general-purpose timing signals provided by the onboard Am9513A Counter/Timer. These signals
are explained under the General-Purpose Timing Signal Connections section later in this chapter.
Data Acquisition Timing Connections
The data acquisition timing signals are SCANCLK, EXTSTROBE*, START TRIG*, STOP
TRIG, and EXTCONV*.
SCANCLK is an output signal that generates a high-to-low edge whenever an A/D conversion
begins. SCANCLK pulses only when scanning is enabled on the AT-MIO-16D. SCANCLK is
normally high and pulses low for approximately 1
µ
sec after the A/D conversion begins. The low-
to-high edge signals that the input signal has been acquired. This signal can be used to clock
external analog input multiplexers. The SCANCLK signal is driven by one LS TTL gate.
A low pulse is generated on the EXTSTROBE* pin when the External Strobe Register is loaded
(see the External Strobe Register section in Chapter 4, Programming). Figure 2-33 shows the
timing for the EXTSTROBE* signal.
t
w
approx. 200 nsec
V
OH
t
w
V
OL
-
Figure 2-33. EXTSTROBE* Signal Timing