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Chapter 7
Counters
specifies pulse specifications that are updated with each sample clock. When a sample clock
occurs, the current pulse finishes generation and the next pulse uses the next sample
specifications.
Frequency Generation
You can generate a frequency by using a counter in pulse train generation mode or by using the
frequency generator circuit, as described in the
section.
Using the Frequency Generator
The frequency generator can output a square wave at many different frequencies. The frequency
generator is independent of the four general-purpose 32-bit counter/timer modules on X Series
devices.
Figure 7-36 shows a block diagram of the frequency generator.
Figure 7-36.
Frequency Generator Block Diagram
The frequency generator generates the Frequency Output signal. The Frequency Output signal
is the Frequency Output Timebase divided by a number you select from 1 to 16. The Frequency
Output Timebase can be either the 20 MHz Timebase, the 20 MHz Timebase divided by 2, or
the 100 kHz Timebase.
The duty cycle of Frequency Output is 50% if the divider is either 1 or an even number. For an
odd divider, suppose the divider is set to D. In this case, Frequency Output is low for (D + 1)/2
cycles and high for (D - 1)/2 cycles of the Frequency Output Timebase.
Figure 7-37 shows the output waveform of the frequency generator when the divider is set to 5.
Figure 7-37.
Frequency Generator Output Waveform
Frequency Output can be routed out to any PFI <0..15> or RTSI <0..7> terminal. All PFI
terminals are set to high-impedance at startup. The FREQ OUT signal can also be routed to many
internal timing signals.
100 kHz Time
bas
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20 MHz Time
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Fre
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ency
O
u
tp
u
t
Time
bas
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FREQ OUT
Divi
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or
(1–16)
Fre
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ency Gener
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÷
2
Fre
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ency
O
u
tp
u
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Time
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FREQ OUT
(Divi
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or = 5)
Summary of Contents for 6368
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