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Chapter 7
Counters
Finite Pulse Train Generation
This function generates a train of pulses of predetermined duration. This counter operation
requires both counters. The first counter (for this example, Counter 0) generates a pulse of
desired width. The second counter, Counter 1, generates the pulse train, which is gated by the
pulse of the first counter. The routing is done internally. Figure 7-26 shows an example finite
pulse train timing diagram.
Figure 7-26.
Finite Pulse Train Timing Diagram
Frequency Generation
You can generate a frequency by using a counter in pulse train generation mode or by using the
frequency generator circuit, as described in the
section.
Using the Frequency Generator
The frequency generator can output a square wave at many different frequencies. The frequency
generator is independent of the two general-purpose 32-bit counter/timer modules on M Series
devices.
Figure 7-27 shows a block diagram of the frequency generator.
Figure 7-27.
Frequency Generator Block Diagram
The frequency generator generates the Frequency Output signal. The Frequency Output signal
is the Frequency Output Timebase divided by a number you select from 1 to 16. The Frequency
Output Timebase can be either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase.
The duty cycle of Frequency Output is 50% if the divider is either 1 or an even number. For an
odd divider, suppose the divider is set to D. In this case, Frequency Output is low for (D + 1)/2
cycles and high for (D - 1)/2 cycles of the Frequency Output Timebase.
Co
u
nter 0
(P
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ired Co
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nter)
Co
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nter 1
Gener
a
tion
Complete
100 kHz Time
bas
e
20 MHz Time
bas
e
Fre
qu
ency
O
u
tp
u
t
Time
bas
e
FREQ OUT
Divi
s
or
(1–16)
Fre
qu
ency Gener
a
tor
÷
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