NI 5772 Component-Level Intellectual Property
(CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but also allows
the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the
external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and the CLIP.
Figure 4. CLIP and FPGA VI Relationship
Adapter Module
CLIP Socket
LabVIEW
FPGA VI
User-Defined
CLIP
NI FlexRIO FPGA Module
FPGA
Exter
nal
I/O Connector
Adapter
Module
Socketed
CLIP
User-Defined
CLIP
Fixed I/O
DRAM 0
CLIP Socket
Socketed
CLIP
DRAM 1
CLIP Socket
Socketed
CLIP
Fix
ed I/O
Fix
ed I/O
DRAM 0
DRAM 1
The NI 5772 ships with socketed CLIP items that add module I/O to the LabVIEW project.
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