Figure 7. NI 5772SampleAcq (FPGA).vi Block Diagram
20. Save the VI as
5772SampleAcq(Host).vi
.
21. Click the
Run
button. LabVIEW creates a default build specification and begins
compiling the VI. The
Generating Intermediate Files
window opens and displays the
code generation progress. Next, the
Compilation Status
window opens and displays the
progress of the compilation. The compilation takes several minutes.
22. Click
Close
in the
Compilation Status
window.
23. Save and close the VI.
24. Save the project.
Creating a Host VI
1.
In the
Project Explorer
window, right-click
My Computer
and select
New
»
VI
to open
a blank VI.
2.
Select
Window
»
Show Block Diagram
to open the VI block diagram.
3.
Place the Open FPGA VI Reference function, located on the
FPGA Interface
palette, on
the block diagram.
4.
Right-click the Open FPGA VI Reference function, and select
Configure Open FPGA
VI Reference
.
5.
In the
Configure Open FPGA VI Reference
dialog box, select
VI
in the
Open
section.
6.
In the
Select VI
dialog box that opens, select
5772SampleAcq (FPGA).vi
under your
device and click
OK
.
7.
Click
OK
in the
Configure Open FPGA VI Reference
dialog box. The target name
appears under the Open FPGA VI Reference function in the block diagram.
8.
Add a While Loop to the block diagram. Place the While Loop to the right of the Open
FPGA VI Reference function.
9.
Right-click the conditional terminal inside the While Loop, and select
Create Control
to
create a STOP button on the VI front panel window.
10. Add the Read/Write Control function, located on the
FPGA Interface
palette, inside the
While Loop.
11. Wire the
FPGA VI Reference Out
output of the Open FPGA VI Reference function to
the
FPGA VI Reference In
input on the
Read/Write Control
function.
12. Wire the
error out
output of the Open FPGA VI Reference function to the
error in
input
of the
Read/Write Control
function.
NI 5772R User Manual and Specifications | © National Instruments | 15