
PIN CONFIGURATION
V
SS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V
DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
DQ7
LDQM
V
SS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
VDDQ
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
V
DD
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
27
26
DQ7
LDQM
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.
CS
Chip Select
Command input enable or mask except CLK, CKE and DQM
BA
Bank Address
Select either one of banks during both RAS and CAS activity.
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation.
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuit and input buffer
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for DQ
NC
No Connection
No connection
SD RAM : IC47
2
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21
Summary of Contents for VISO TWO
Page 1: ... 5 6 2 3 6 2ECEIVER 6 3 47 6 2ECEIVER 6 3 47 Before SN A9YVISOTWO06301 ...
Page 6: ...1 7 9 ...
Page 7: ...1 8 Ê Ê ...
Page 8: ...EXPLODED VIEW AH VER before SN A9YVISOTWO06301 1 9 1 10 ...
Page 10: ...EXPLODED VIEW C VER before SN A9YVISOTWO06301 1 12 1 13 ...
Page 21: ...isvjr kphnyht 2 10 CODEC DIR AK4589 IC44 ...
Page 22: ...PIN DESCRIPTION 2 11 ...
Page 23: ...2 12 PIN DESCRIPTION ...
Page 24: ...2 13 PIN DESCRIPTION ...
Page 25: ...VOLUME FUNCTION BD3816K1 IC31 2 14 ...
Page 26: ...2 15 ...
Page 35: ...SLQ DVVLJQPHQW 2 24 Motor Driver IC AM5888 IC16 ...
Page 36: ...2 25 ...
Page 43: ...OR GATE IC48 74LCX32TTR Pin Connection And IEC Logic Symbols 2 32 ...
Page 47: ...EEPROM IC22 AT24C08N10SC 2 36 ...
Page 49: ...Pin Assignment Block Diagram RDS DEMODULATION IC LC72723M IC29 2 38 ...
Page 58: ...1 BLOCK DIAGRAM 2 47 2 48 ...
Page 59: ...2 WIRING DIAGRAM before SN A9YVISOTWO06301 2 49 2 50 ...
Page 61: ...MCU INPUT PART before SN A9YVISOTWO06301 2 53 2 54 ...
Page 62: ...DSP CODEC PART 2 55 2 56 ...
Page 67: ...MPEG PART 2 65 2 66 ...
Page 68: ...4 PRINTED CIRCUIT BOARDS FRONT BOARD before SN A9YVISOTWO06301 2 67 2 68 ...
Page 69: ...INPUT BOARD TOP VIEW before SN A9YVISOTWO06301 2 69 2 70 ...
Page 70: ...INPUT BOARD BOTTOM VIEW before SN A9YVISOTWO06301 2 71 2 72 ...
Page 73: ...MPEG BOARD TOP VIEW 2 77 2 78 ...
Page 74: ...MPEG BOARD BOTTOM VIEW 2 79 2 80 ...
Page 103: ... 5 6 2 3 42 3 4 2 4 4 2 4 1 6 2ECEIVER 6 3 47 ...