
Pin
#
Pin Name
Direct-
ion
Function
in Slave Mode
Function
in Master Mode
Notes
32 HSDP_DATA
S=In
M=Out
High Speed Data Port Data
Input
High Speed Data Port Data
Output
Out= 4mA, SLC
In=LVTTL S/T
34 HSDP_CLK
S=In
M=Out
High Speed Data Port Clock
Input
High Speed Data Port Clock
Output
Out= 4mA, SLC
In=LVTTL S/T
35 DT4_MODE
S=In
M=In
Enables/Disables driver on
SC_RATE and ANT_REV
(High = enable driver) This
pin was VSS on rev 3
XM/DT IC
Enables/Disables drivers on
MUTE and ANT_REV (High
= enable drivers) This pin
was VSS on rev 3 XM/DT IC
In=LVTTL S/T
36 HSDP_EN#
S=In
M=Out
High Speed Data Port Enable
Input (Active low)
High Speed Data Port Enable
Output (Active low)
Out= 4mA, SLC
In=LVTTL S/T
37 I2S_DATA
S=In
M=Out
I2S Digital Audio Port Data In
I2S Digital Audio Port Data
Out
Out= 4mA, SLC
In=LVTTL S/T
39 I2S_SCLK
S=In
M=Out
I2S Digital Audio Port Bit
Clock In
I2S Digital Audio Port Bit
Clock Out
Out= 4mA, SLC
In=LVTTL S/T
41 I2S_LRCLK
S=In
M=Out
I2S Digital Audio Port
Left/Right Clock In
I2S Digital Audio Port
Left/Right Clock Out
Out= 4mA, SLC
In=LVTTL S/T
43 I2S_OCLK
S=In
M=Out
I2S Digital Audio Port
Oversample Clock
(not used, leave unconnected)
I2S Digital Audio Port
Oversample Clock Out
Out= 4mA, SLC
44 MUTE
S=n/u
M=Out
Not used in Slave mode, leave
unconnected
Provides a mechanism for
muting the audio during an
I2S rate change (High=mute)
Out= 4mA, SLC
45 SAII_CLK
S=Out
M=In
SAII Port Clock Output
SAII Port Clock Input
Out= 4mA, SLC
In=LVTTL S/T
47 SAII_DATA
S=Out
M=In
SAII Port Data Output
SAII Port Data Input
Out= 4mA, SLC
In=LVTTL S/T
48 SAII_REQ
S=In
M=Out
SAII Port Request Input
SAII Port Request Output
Out= 4mA, SLC
In=LVTTL S/T
Pin#
Pin Name
Type
Function
in Slave Mode
Function
in Master Mode
Notes
4, 8, 17, 20,
27, 33, 40, 46
VDD
PWR
+3.3V Supply Voltage
+3.3V Supply Voltage
2, 10, 16, 21,
24, 25, 31, 38,
42
VSS
GND
Digital Ground
Digital Ground
Notes: All Inputs are 3.3V LVTTL compatible; S/T = Schmitt Trigger inputs; SLC = Slew Rate Controller Output
2
-
20
Summary of Contents for VISO TWO
Page 1: ... 5 6 2 3 6 2ECEIVER 6 3 47 6 2ECEIVER 6 3 47 Before SN A9YVISOTWO06301 ...
Page 6: ...1 7 9 ...
Page 7: ...1 8 Ê Ê ...
Page 8: ...EXPLODED VIEW AH VER before SN A9YVISOTWO06301 1 9 1 10 ...
Page 10: ...EXPLODED VIEW C VER before SN A9YVISOTWO06301 1 12 1 13 ...
Page 21: ...isvjr kphnyht 2 10 CODEC DIR AK4589 IC44 ...
Page 22: ...PIN DESCRIPTION 2 11 ...
Page 23: ...2 12 PIN DESCRIPTION ...
Page 24: ...2 13 PIN DESCRIPTION ...
Page 25: ...VOLUME FUNCTION BD3816K1 IC31 2 14 ...
Page 26: ...2 15 ...
Page 35: ...SLQ DVVLJQPHQW 2 24 Motor Driver IC AM5888 IC16 ...
Page 36: ...2 25 ...
Page 43: ...OR GATE IC48 74LCX32TTR Pin Connection And IEC Logic Symbols 2 32 ...
Page 47: ...EEPROM IC22 AT24C08N10SC 2 36 ...
Page 49: ...Pin Assignment Block Diagram RDS DEMODULATION IC LC72723M IC29 2 38 ...
Page 58: ...1 BLOCK DIAGRAM 2 47 2 48 ...
Page 59: ...2 WIRING DIAGRAM before SN A9YVISOTWO06301 2 49 2 50 ...
Page 61: ...MCU INPUT PART before SN A9YVISOTWO06301 2 53 2 54 ...
Page 62: ...DSP CODEC PART 2 55 2 56 ...
Page 67: ...MPEG PART 2 65 2 66 ...
Page 68: ...4 PRINTED CIRCUIT BOARDS FRONT BOARD before SN A9YVISOTWO06301 2 67 2 68 ...
Page 69: ...INPUT BOARD TOP VIEW before SN A9YVISOTWO06301 2 69 2 70 ...
Page 70: ...INPUT BOARD BOTTOM VIEW before SN A9YVISOTWO06301 2 71 2 72 ...
Page 73: ...MPEG BOARD TOP VIEW 2 77 2 78 ...
Page 74: ...MPEG BOARD BOTTOM VIEW 2 79 2 80 ...
Page 103: ... 5 6 2 3 42 3 4 2 4 4 2 4 1 6 2ECEIVER 6 3 47 ...