NAD M56, Service Manual

Page: 70 / 101

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5. BCM7601-1 CIRCUIT DIAGRAM
CLK27_XTALP C3
DGND
CLK27_XTALN C3
CLK27_XTALP D2
CLK27_XTALN
D2
C532
22uF
PLL_AVDD12
DGND
VCC_1V2
PLL_AVDD12
DGND
VDAC_CVBS 6:D4
R501 562(1%)
DGND
VDAC_VDD33
L501
HB2012_1000
VCC_3V3
C529
22uF
VDAC_VDD33
AUD0_SPDIF
H6;6:J2
VCC_1V2
USB_VDD12
DGND
L506
HB2012_1000
VCC_3V3
IC502
MCP1319-29
1
RST
2
VSS
3
RST
4
MR
5
VDD
DGND
DGND
DGND
VCC_3V3
TP517
CA501
22uF/16V
DGND
VCC_3V3
I2S_CLK 4:D7
I2S_LRCLK 4:D7
I2S_DATA0 4:D7
I2S_DATA2
4:D7;H6
I2S_DATA1 4:D7
I2S_DATA3
4:D7;H6
SGPIO01/BSC_M0_SDA 4:F5;G2
SGPIO00/BSC_M0_SCL 4:F5;G3
SGPIO00/BSC_M0_SCL 4:F5;F4
SGPIO01/BSC_M0_SDA 4:F5;F3
VCC_3V3
TP594
EPHY_RDP
4:J6
EPHY_TDP 4:J6
EPHY_TDN 4:J6
TP5A8
CLK33_OUT_PCI_CLK_IN 2:F3
VDAC_Y 6:F5
VDAC_Pb 6:F5
VDAC_Pr 6:F5
DGND
X504
27MHz/18pFCL
C520
0.1uF
C523
0.1uF
C510
0.1uF
C515
0.1uF
R591
OPEN
R531
10k
R5D7
OPEN
R509 OPEN_1k
C522
OPEN_0.1uF
L512
4.7UH
R534
10k
R539
10k
C504
30pF
C518
30pF
R511
18
R518
18
R5A1
1.2K
R5A0
1.2K
R5C8 33
R533
OPEN
R521
10k
R537
10k
R581
10k
R552
OPEN
R5E0
10k
R589
10k
R592
10k
R522
10k
R535
10k
R5E9
OPEN
R508
OPEN_4.7k
R5D5
10k
GPIO_19_UART_PROTECTION 4:H8
DGND
TP518
TP519
TP520
TP521
TP522
BSC_S_SCL 4:F3
BSC_S_SDA 4:F3
DGND
VDAC_VDD33
C533 0.1uF
C534 0.01uF
C535 0.1uF
C536 0.01uF
HDMI_SCL 6:I6
HDMI_SDA 6:I6
HDMI_0_N 6:I6
HDMI_0_P 6:I7
HDMI_1_N 6:I7
HDMI_1_P 6:I7
HDMI_CLK_N 6:I6
HDMI_2_N
6:I7
HDMI_2_P 6:I7
HDMI_CLK_P 6:I6
HDMI_PVDD12
DGND
R553 12K(1%)
DGND
R554 27K
HDMI_HTPLG 6:I6
AUD_FS_CLK0
4:B7;6:B5
I2S_S_CLK
6:B6
I2S_S_DATA
H6;6:B6
I2S_S_LR
6:B6
R555
33
R556 33
R557 33
R558 33
R559 33 R560 33
R561 33
R562 33
R563 33
R564
33
R565
33
USB_VDD12
DGND
USB0_PWRON 4:B4;H6
USB0_DN
4:B5
USB0_PWRFLT
4:B4
USB0_DP 4:B5
USB1_DN
4:B4
USB1_PWRFLT 4:B4
USB1_PWRON 4:B4
USB1_DP
4:B5
DGND
SATA_RXDP1 4:I2
SATA_TXDP1 4:I2
SATA_TXDN1 4:I2
SATA_RXDN1 4:I2
DGND
SATA_PLLVDD12
C538
0.1uF
SATA_PLLVDD12
L513
HB2012_1000
C537
22uF
VCC_1V2
DGND
DGND
R567 1.24K(1%)
DGND
EPHY_VDD12
STANDBY_BTN/SGPIO_02 F3;G3
nRESET
4:J5;E7
UART_RX0 4:H7
UART_TX0
4:H7;H6
UART_RX1 4:G8
UART_TX1
4:G8;H6
UART_RX2
4:I8
UART_TX2
4:I8;H6
UART_RX3 4:F6
UART_TX3 4:F6
STANDBY/GPIO_07
G3
PSU_ON/GPIO_13 7:B5
STANDBY_BTN/SGPIO_02 F4;G3
EJECT_BTN/SGPIO_03
G3
nSELF_RST/GPIO_14 E7
R569
10K
EJECT_BTN/SGPIO_03
F3
STANDBY_BTN/SGPIO_02 F3;F4
nRESET 4:J5;F4
TP523
R570 OPEN
nSELF_RST/GPIO_14
F3
R571
OPEN
EBI_ADDR[24] 2:G3
EBI_nRW 2:F3
EBI_nWE1 2:F3
EBI_nWE0 2:F3;4:B2
PCI_nGNT0
2:F3
NAND_nRE 2:F2;4:B2
NAND_CLE
2:F2;4:B2
EBI_ADDR[25] 2:G3
NAND_ALE
2:F2;4:B2
USB0_PWRON 4:B4;F5
I2S_DATA2 4:D7;C5
I2S_DATA3 4:D7;C5
I2S_S_DATA F5;6:B6
AUD0_SPDIF
F5;6:J2
UART_TX1 4:G8;F4
UART_TX2 4:I8;F4
UART_TX0 4:H7;F4
R572
10k
R573
OPEN
R574
10k
R575
OPEN
R576
OPEN
R577
OPEN
R578
10k
R587
OPEN
R582
10k
R583
OPEN
R584
10k
R585
OPEN
R586
OPEN
C539 100pF
C540
0.1uF
L514
HB2012_1000
DGND
VCC_1V2
EPHY_VDD12
C541
OPEN_22uF
R588 0
VCC_1V2
L515
HB2012_1000
C543
0.1uF
DGND
C544
OPEN_22uF
HDMI_PVDD12
TP5B0
TP5A9
TP5B3
STANDBY/GPIO_07 F3
EPHY_RDN
4:J7
DGND
RESET_AUDIO_CARD/GPIO_12 4:E8
R5F0
75(1%)
R5F1
75(1%)
R5F2
75(1%)
R5F3
75(1%)
DGND
R5F4 1k
AUD_MUTE/GPIO_06
6:B5
TP5B1
IC201
BCM7601 BGA 507Pin (21 x 21) Broadcom
B13
CLK27_XTALN
C13
CLK27_XTALP
E13
ALT27_XTALN
E12
ALT27_XTALP
H19
ALT_XTAL_SEL
G13
PLL_AVDD12
F13
PLL_AVSS
G15
CLK33_OUT
D13
PLL_TESTOUT
D16
BYP_SYS800_PLL
A14
BYP_CPU_CLK
C15
BYP_216_CLK
C16
BYP_SYS9_CLK
E15
BYP_AVD_CLK
B14
BYP_DSP_CLK
E16
TEST_MODE0
F16
TEST_MODE1
B16
TEST_MODE2
A16
TEST_MODE3
G14
EJTAG_nTRST
A13
EJTAG_TMS
D14
EJTAG_TCK
E14
EJTAG_TDI
F15
EJTAG_TDO
C14
EJTAG_CE
D22
BSC_S_SCL
C22
BSC_S_SDA
F10
VDAC0_REG
E10
VDAC1_REG
G10
VDAC_AVSS
A12
VDAC_AVSS
G11
VDAC_AVDD33
E7
HDMI_SCL
F7
HDMI_SDA
A9
HDMI_0_P
B9
HDMI_0_N
D8
HDMI_1_P
D9
HDMI_1_N
A8
HDMI_2_P
B8
HDMI_2_N
C9
HDMI_CLK_P
C10
HDMI_CLK_N
G9
HDMI_PDVDD12
F8
HDMI_PLLCAP
D7
HDMI_EXT12K
A10
HDMI_GND
E8
HDMI_CEC_RES
C8
HDMI_CEC
C7
HDMI_HTPLG
Y21
I2S_CLOCK
U23
I2S_LR
U21
I2S_DATA0
U20
I2S_DATA1
U22
I2S_DATA2
AA25
I2S_DATA3
V20
AUD_FS_CLK0
U25
AUD0_SPDIF
Y22
I2S_S_CLK
V25
I2S_S_LR
AC22
I2S_S_DATA
F5
USB_PLLVDD12
D1
USB_AVSS
B4
USB_MONPLL
C2
USB_MONCDR
E4
USB0_DP
E3
USB0_DN
B2
USB0_PWRON
C4
USB0_PWRFLT
D3
USB1_DP
D2
USB1_DN
D4
USB1_PWRON
B3
USB1_PWRFLT
C3
USB_RREF
B5
SATA_RXDP
A5
SATA_RXDN
B6
SATA_TXDP
A6
SATA_TXDN
C5
SATA_PLLTESTP
C6
SATA_PLLTESTN
H7
SATA_PLLVDD12
A4
SATA_AVSS
J7
EPHY_AVDD12
F1
EPHY_AGND
K7
EPHY_ATEST
F3
EPHY_RDAC
G5
EPHY_RDN
G6
EPHY_RDP
F4
EPHY_TDN
G4
EPHY_TDP
B23
IR_IN0
A20
IR_OUT
B22
nRESET
G20
nFP_4SEC_RESET
G19
nRESET_OUT
V23
UART_RX0
W22
UART_TX0
V21
UART_RX1
AA22
UART_TX1
AA23
UART_RX2_GPIO_04
AB21
UART_TX2_GPIO_05
V22
UART_RX2_GPIO_16
U19
UART_TX2_GPIO_15
T19
BSC_M_SCL0
T22
BSC_M_SDA0
AB25
GPIO_06
W23
GPIO_07
Y23
GPIO_09
AB24
GPIO_10
AA21
GPIO_11
V19
GPIO_12
AB23
GPIO_13
AA24
GPIO_14
Y25
GPIO_19
V24
SGPIO_02
T20
SGPIO_03
E11
VDAC1_0
C12
VDAC0_0
F11
VDAC1_1
B12
VDAC0_1
D11
VDAC1_2
D12
VDAC0_2
D10
VDAC_RBIAS
R566 3.9K(1%)
R568
10K
BCM7601 STRAP OPTIONS
n o i t p i r c s e D e m a N d l e i F Signal
Strap_use_defaults
0:All straps must be set on board
1:Only non-default values need be set
EBI_nRW
Value
1
strap_reset_outb_def_value internal(Hard coded)
Default value of the nRESET_OUT pin after hardware reset
After hardware reset, the nRESET_OUT will change to 1(deasserted)
EBI_addr24
EBI_addr25
strap_test_debug_en_1 0
e u l a v n w o n k n u n a s n r u t e r d a e r A . 0 h t i w n e t t i r w e b t s u m t i b d e v r e s e R A / N d e v r e s e R 0
0
33MHz clock is used
strap_xtal_sel
strap_xtal_adj_3
strap_xtal_adj_2
strap_xtal_adj_1
strap_xtal_adj_0
strap_ebi_rom_size_1
strap_ebi_rom_size_0 NAND_nRE
NAND_CLE
s s e r d d a I B E t r e v n i t o n o D = 0 r d d a _ t r e v n i _ i b e _ p a r t s 0
1=invert upper bits of EBI address(not used by NAND flash)
USB0_PWRON
0
0
Test debug mode select
Security related(2 bits)? default=0
0 strap_pci_ext_arb
I2S_S_DATA
strap_ebi_cs_swap
PCI_nGNT0 0
strap_pci_memwin_size_1
strap_pci_memwin_size_0 0
0=Chip is a PCI master device
1=Chip operates as a PCI slave device
strap_pci_memwin2_en
strap_pci_memwin1_en
strap_pci_client
0:system is LITTLE endian
1:system is BIG endian
1
0
0
5. BCM7601-1
These configuration resistors do not need to be close to the BCM7601.
So place them at the destination of the trace.
2009.2.16
Close to 7601 and avoid heat sink
Must be placed near BCM7601
Place under the
BCM7601 near ball
strap_test_debug_en_0
strap_33_27_mhz_clock
Reserved
Reserved
Reserved
strap_flash_width
strap_system_big_endian
strap_spi_slave_enable
Reserved
Reserved
Reserved
bit
internal(Hard coded)
N/A
Refer to
pin ALT_XTAL_SEL
I2S_DATA2
I2S_DATA3
N/A
N/A
internal(Hard coded)
EBI_nWE0
internal(Hard coded)
internal(Hard coded)
internal(Hard coded)
internal(Hard coded)
internal(Hard coded)
NAND_ALE
N/A
N/A
N/A
strap_reset_ext_mode AUD0_SPDIF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
Reserved bit must be written with 0. A read returns an unknown value
XTAL select
XTAL adjustment
NOR ROM(always 64MB window): NAND ROM:
0=NOR flash 0=disable ECC
1=OneNAND flash 1=1 bit ECC
2=reserved 2=4 bit ECC
3=reserved 3=8 bit ECC
Reserved bit must be written with 0. A read returns an unknown value
internal Arb.(default)
NOR ROM: NAND ROM:
0=8bit 0=allow writes to block 0
1=16bit 1=ignor write commands to block 0(disallow writes)
0=no swap
1=swap cs_0 and cs_1
0=The slave serial port(SSP) uses BSC protocol
1=The SSP uses SPI protocol
1024MB
PCI memory window 2 is disabled
PCI memory window 1 is enabled
Reserved bit must be written with 0. A read returns an unknown value
0=nRESET_OUT is not extended
1=nRESET_OUT is extended 200ms
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
R O N m o r f t o o B = 0 0 1 h s a l f _ d n a n _ p a r t s
1=Boot from NAND
EBI_nWE1 1
Close to 7601