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Manual SDs-01 E 3.2.2003 18:26 Uhr Seite 15
Technical Data
AES/EBU INPUT
Interface
1 x XLR female, transformer balanced, input impedance 110
Ω
, 200 mV – 7.0 V
Format
AES3 – 1992/2003 and AES11 – 1997/2003
Resolution
16 – 24 bits
Lock range
Every digital audio clock rate from 32.0kHz to 192.0kHz
AES/EBUid INPUT
Interface
1 x BNC female, unbalanced, input impedance 75
Ω
, 200 mV – 7.0 V
Format
AES3id – 1995/2001
Resolution
16 – 24 bits
Lock range
Every digital audio clock rate from 32.0 kHz to 192.0 kHz
AES/EBU OUTPUTs 1 – 6
Interface
6 x XLR male, transformer balanced, 3.5 Vpp @ 110
Ω
, output impedance 110
Ω,
buffered
Format
AES3 – 1992/2003 and AES11 – 1997/2003
Resolution
16 – 24 bits
Transmitted audio clock rates
Every digital audio clock rate from 32.0kHz to 192.0kHz
AES/EBUid OUTPUTs 1 + 2
Interface
2 x BNC female, unbalanced, 1.0 / 3.0 Vpp @ 75
Ω
, output impedance 75
Ω,
buffered
Format
AES3id – 1995/2001
Resolution
16 – 24 bits
Transmitted audio clock rates
Every digital audio clock rate from 32.0kHz to 192.0kHz
SIGNAL PROCESSING
Signal processes
AES/EBU to AES/EBUid + AES/EBUid to AES/EBU electrical conversion
Signal stabilization and refreshing by low-jitter PLL
Clock rate analyzing
Automatic clock rate detection of the incoming reference signal between
32.0 kHz and 192.0 kHz in all operation modes.
POWER SUPPLY
Type
Internal, switching power supply
Input voltage
90 V – 260 V (automatic adjustment), 47 Hz – 440 Hz
Power consumption
max. 10 W
SYSTEM UNIT COVER
Cover size / material / color
196 x 42 x 156mm without connectors (W x H x D), aluminium sheet 1mm, black
Front panel size / material
198 x 44 x 2mm (W x H x D), aluminium
Weight
~ 1210g
19
