
www.RFM.com
© 2010-2012 by RF Monolithics, Inc.
Technical s1.678.684.2000
E-mail:
Page 52 of 80
DNT90 Integration Guide - 08/09/12
GpioAlt
bit is set for GPIO4, the corresponding
GpioSleepMode
bit is ignored and GPIO4 is controlled
directly by the
GpioSleepState
parameter bit 7.
GpioSleepDir
- when
GpioSleepMode
is enabled, this parameter functions to set the direction of the
GPIOs during a device’s sleep period. This enables the user to provide alternate configurations during
sleep that will help minimize current consumption. Bits 0..5 correspond to GPIO0..GPIO5. Setting a
GpioSleepDir
bit to 1 to specifies an output; 0 specifies an input.
GpioSleepState
- when
GpioSleepMode
is enabled, this parameter functions as a bitmask to control the
states of the GPIOs, the RADIO_TXD output, and the /HOST_CTS and /DCD outputs during a device’s
sleep period. This allows the user to set alternate configurations during sleep to minimize current con-
sumption. Bits 0..5 correspond to GPIO0..GPIO5 respectively. Bit 6 sets the state of RADIO_TXD, and bit
7 sets the states of /HOST_CTS and /DCD. A sleep state bit is set to 1 to specify a high output or an in-
ternal pull-up on an input, or to 0 to specify a low output or no internal pull-up on an input. Bit 6 must be
set low in order to achieve minimum sleep current (high impedance load assumed), and the other bits
may need to be set low or high depending on their external loads. When bit 6 is set low, expect a serial
“break” condition to occur as the module wakes from sleep. The serial break condition can be eliminated
by setting bit 6 high, but sleep current will be increased.
Dac0Init
- this parameter sets the initial value for DAC0 at startup.
Dac1Init
- this parameter sets the initial value for DAC1 at startup.
AdcSampleIntvl
- this parameter sets the frequency (sample interval) of ADC measurements used to de-
termine if a threshold has been exceeded or in calculating an average measurement value. The ADC
channels are read on each ADC cycle, along with the states of GPIO2 and GPIO3. Each
AdcSampleIntvl
count equals 10 ms. The default is 100 ms. This interval will be the worst-case latency for ADC generated
interrupts. Note that
AdcSampleIntvl
is independent of
IoReportInterval
as the ADCs are read on both
intervals.
Adc0..2ThresholdLo/Hi
- these parameters set the thresholds to trigger an I/O report based on ADC
measurements. If I/O reporting is enabled, a single event report containing the contents of the I/O bank is
generated when a threshold is crossed. Reporting is edge-triggered with respect to threshold boundaries,
not level-triggered. Additional reports are not triggered unless the ADC measurement first returns inside
the threshold boundary and then crosses the threshold again. Triggers occur whenever one of the follow-
ing inequalities is satisfied:
ADC
x
< ADC
x
_ThresholdLo
ADC
x
> ADC
x
_ThresholdHi
IoReportTrigger
- a trigger event on any enabled trigger source will cause a DNT90E router or remote to
send an event message to the base containing the entire current values of the Bank 5.
bit 7
ADC2 high/low thresholds
bit 6
ADC1 high/low thresholds
bit 5
ADC0 high/low thresholds
bit 4
Periodic timer
bit 3
GPIO3 edge
bit 2
GPIO2 edge
bit 1
GPIO1 edge
bit 0
GPIO0 edge
I/O reporting is supported for remotes and routers only, not the base.